Taura 综合征病毒主要结构蛋白的表达与纯化

根据Taura综合征病毒(TSV)基因组,设计特异性引物,从感染病毒组织中提取组织总RNA后扩增,分别将3个主要结构蛋白基因VP1、VP2和VP3克隆到pGEM TEasyVector.与表达载体连接后,导入大肠杆菌中诱导表达,并纯化目的蛋白.诱导表达的融合蛋白分子量分别为54.2×103、43×103和57.1×103,在变性条件下过柱纯化VP1和VP2,一次可以纯化10mg以上纯度较高的蛋白.     

Stress evaluation of Through-Silicon Vias using micro-infrared photoelasticity and finite element analysis

The Through-SiliconVias (TSV) is a key component of three dimensional electronic packaging. Obtaining its stresses is very important for evaluating its reliability. A micro-infrared photoelasticity system with a thermal loading function was built and applied to characterize the stresses of the TSV structure. Through testing it was found that the stress of each TSV is different even if their fabrication technology is exactly the same, that different TSVs obtain their stress free states at different elevated temperatures, and that their stress free states are maintained even when the temperature is further elevated. A finite element model was used to quantitatively determine the stresses of a TSV under different stress-free temperatures. Different virtual photoelasticity fringe patterns were then created based on the principle of photoelasticity and the simulated stresses. Comparing the virtual fringe patterns with the experimental pattern, an appropriate virtual photoelasticity fringe pattern and the corresponding stresses of TSV were determined     

一种考虑硅通孔电阻-电容效应的三维互连线模型

硅通孔(TSV)是三维集成电路的一种主流技术.基于TSV寄生参数提取模型,对不同物理尺寸的TSV电阻-电容(RC)参数进行提取,采用Q3D仿真结果验证了模型精度.分析TSVRC效应对片上系统的性能及功耗影响,推导了插入缓冲器的三维互连线延时与功耗的解析模型.在45nm互补金属氧化物半导体工艺下,对不同规模的互连电路进行了比较分析.模拟结果显示,TSVRC效应导致互连延时平均增加10%,互连功耗密度平均提高21%;电路规模越小,TSV影响愈加显著.在三维片上系统前端设计中,包含TSV寄生参数的互连模型将有助于设计者更加精确地预测片上互连性能.     

Development of a BGA Package Based on Si Interposer with Through Silicon Via

A ball grid array (BGA) package based on Si interposer with through silicon via (TSV) was designed. Thermal behaviors of the designed BGA with Si interposer has been analyzed and compared to a conventional BGA with BT substrate in the approach of finite element modeling (FEM). The Si interposer with TSV was then fabricated and the designed BGA package was demonstrated. The designed BGA package includes a 100 μm thick Si interposer, which has redistribution copper traces on both sides. Through vias with 25 to 40 μm diameter were fabricated on the Si interposer using deep reactive ion etching (DRIE), plasma enhanced chemical vapor deposition (PECVD), copper electroplating and chemical mechanical polishing (CMP), etc. TSV in the designed interposer is used as electrical interconnections and cooling channels. 5 mm by 5 mm and 10 mm by 10 mm thermal chips were assembled on the Si interposer.     

BCB介质层同轴TSV的热力学仿真分析

穿透硅通孔（through silicon via,TSV）的热机械可靠性问题已经成为制约TSV市场化应用的重要因素.本文对BCB介质层同轴TSV的热力学特性进行了研究分析,同时对其几何参数（SiO₂绝缘层厚度、屏蔽环厚度、TSV间距、中心信号线半径）进行了变参分析,为降低热应力提供指导意见.结果表明,在阻抗匹配的前提下,通过增加SiO₂绝缘层厚度、减小屏蔽环厚度能够有效降低同轴TSV的诱导热应力;相比之下中心信号线半径和TSV间距的变化对其影响可忽略不计.      

低阻硅TSV与铜填充TSV热力学特性对比分析

对低阻硅TSV以及铜填充TSV的热力学性能通过有限元仿真的方法进行对比分析.低阻硅TSV在绝缘层上方以及低阻硅柱上方的铝层区域中凸起最为显著,且高度分别为82 nm和76 nm;铜填充TSV的凸起位置主要集中在通孔中心铜柱的上方,最大值为150 nm.应力方面,低阻硅TSV在绝缘层两侧的应力最大,且最大值为1 005 MPa;铜填充TSV在中心铜柱外侧应力最大,且最大值为1 227 MPa.另外,两种结构TSV的界面应力都在靠近TSV两端时最大.低阻硅TSV界面应力没有超过400 MPa,而铜填充TSV在靠近其两端时界面应力已经超过800 MPa.综上所述,相比于铜填充TSV,低阻硅TSV具有更高的热力学可靠性.      

基于单轴微拉伸的TSV铜力学性能研究

电子产品的微型化趋势使芯片的三维集成概念应运而生,并通过硅通孔(TSV-through silicon via)技术得以实现.为了测试TSV中互连铜(Cu-TSV)的力学性能,提出了1个简便、易于操作的单轴微拉伸方法.利用有限元分析优化设计Cu-TSV微拉伸试样的支撑框架结构,有效减小试样在制作及操作过程中的损伤;种子层采用溅射Ti膜取代传统的溅射Cr/Cu膜,减小了电镀过程中的应力,避免了对种子层碱性刻蚀时对试样的腐蚀;采用单轴微拉伸系统对优化设计与制备的Cu-TSV微拉伸试样进行测试.经测试得到的Cu-TSV的杨氏模量与抗拉强度为25.4～32.9GPa和574～764MPa.     

Sidewall Roughness对TSV互连结构高频性能的影响

本文详细分析了由Bosch 刻蚀形成的侧壁形貌的粗糙度（Sidewall Roughness）对硅通孔（TSV）互连结构高频性能的影响,并通过全波电磁场仿真软件HFSS将粗糙侧壁TSV互连结构与平滑侧壁TSV互连结构的传输特性进行了详尽的对比,仿真结果显示,在相同的条件下,粗糙侧壁TSV结构的插入损耗比光滑侧壁TSV结构增加了15%,并且随着侧壁形貌粗糙度的增加,TSV互连结构的高频性能恶化更加严重。最后,文章通过对二氧化硅绝缘层厚度和TSV直径对TSV互连结构高频性能的影响,提出了补偿侧壁粗糙度对高频性能产生的不良影响的方法,为TSV电学设计提供参考依据。     

TSV立体集成计算机研究进展

分析硅通孔(through-silicon via,TSV)立体集成用于计算机处理芯片的优势.介绍TSV立体集成计算机处理器模块单元指令调度集、KS加法器和对数移位器等的发展现状,以及利用TSV立体集成技术的3D立体架构代替平面架构所带来的功耗降低和性能提升的巨大优势.     

On-wafer thermomechanical characterization of a thin film polyimide formed by vapor deposition polymerization for through-silicon via applications: Comparison to plasma-enhanced chemical vapor deposition SiO2

Thin-film polyimides were prepared by solvent-less vapor deposition polymerization (VDP) from pyromellitic dianhydride and 4,4′-oxydianiline at 200 °C for liner dielectric formation of vertical interconnects called through-silicon vias (TSVs) used in three-dimensionally stacked integrated circuit (3DICs). FTIR, synchrotron XPS, and TDS were employed for determining the imidization ratio, and in addition, the mechanical properties, coefficient of thermal expansion and Young's modulus, of the VDP polyimide were characterized on Si wafers. The VDP polyimide exhibited extremely high conformality, beyond 75%, toward high-aspect-ratio deep Si holes, compared with conventional SiO₂ prepared by plasma-enhanced chemical vapor deposition. The adhesion between the VDP polyimide and Si wafer was enhanced by an Al-chelate promotor. Remarkably, the VDP polyimide TSV liner dielectrics showed much less thermomechanical stresses applied to the Si surrounding the TSVs than the plasma-chemical vapor deposition SiO₂. The small keep-out zone is expected for scaling down highly reliable 3DICs for the upcoming real artificial intelligence society.