基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

智能化中高压变频器实载试验平台的实现

中、高压变频器产量越来越多，但试验手段大多比较落后，一般采用带电机空转的方法。本文介绍了一个高压变频器试验平台，通过该平台可以对电压等级在3kV～10kV、功率在5000kW以下的变频器进行实载试验。     

超高压大容量铝电解电容器的研制

分析了大功率设备用超高压大容量铝电解电容器的特点,通过研制工作电解液、制订制作工艺及零部件设计方案,研制出的超高压大容量铝电解电容器具有损耗角正切小(tgδ为0.25)、承受纹波电流能力强(100 Hz,2.12～27.8 A)及寿命长的特点,耐久性达到85℃,5 000 h。     

NMOS器件两次沟道注入杂质分布和阈电压计算

分别考虑了深浅两次沟道区注入杂质在氧化扩散过程中对表面浓度的贡献。对两次注入杂质的扩散分别提取了扩散系数的氧化增强系数、氧化衰减系数和有效杂地系数，给出了表面浓度与工艺参数之间的模拟关系式，以峰值浓度为强反型条件计算了开启电压，文章还给出了开启电压、氧化条件、不同注入组合之间的关系式。     

A covering construction for packing disjoint copies of the Hoffman‐Singleton graph into K50

In this note we show how coverings induced by voltage assignments can be used to produce packings of disjoint copies of the Hoffman‐Singleton graph into K₅₀. © 2003 Wiley Periodicals, Inc. J Combin Designs 11: 408–412, 2003; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/jcd.10049     

基于Protel DXP的电路仿真设计

Protel DXP是集所有设计工具于一身的电子设计自动化(EDA)软件.文中运用其内嵌的仿真器叙述了分压式偏置电路放大器的仿真设计过程,设计过程简单、方便.在电子线路理论教学过程中引入电路设计仿真环节在不同情况下对电路进行实时分析,不仅可以提高学生的学习兴趣,而且能够在较短时间内加深学生对理论知识的理解;在工程设计过程中利用仿真工具对电路进行即时测试,可以缩短设计周期,提高设计效率.     

低压直流供电电路中高压直流的产生

在由低压直流电源供电的电路中,往往电路的某些部位需要使用高于电源所供的电压,将电源所供的低压转换为较高的电压,常用的方法有3种:自举升压、电感升压、逆变升压。结合实际应用电路对各种升压方法从器件选择、升压原理、升压结果等诸方面进行分析、探讨,解决了总体供电电压不变时,局部高压产生的关键性问题。它对电子电器电路的设计人员有一定的启发作用,对优化电路、遴选器件有较强的参考价值。     

行波管放大器相位噪声的分析及其抑制

主要分析规则调相信号对行波管放大器频谱纯度的影响,并且根据行波管放大器相位噪声产生的过程和原因,提出两种抑制相位噪声的方法.