采用无偏振片反射式LCD及超低功耗驱动技术制造移动显示器件

我们通过对材料和制备条件的精细化处理,生产出一种在低刷新频率下无闪烁和图像迟滞现象的反射式显示器。该显示器的功耗非常低,且可在宽温度范围内工作,是未来移动显示器件的潜力平台。     

On the Development of Analogue Sampled-Data Signal Processing

This paper provides a historical perspective on thedevelopment of analogue sampled-data signal processing circuitsand systems. The evolution, role and current trends in the developmentof analogue sampled-data signal processing systems is surveyed.Firstly, the evolution of integrated circuit based techniques,culminating in the ubiquitous switched-capacitor technique istraced. Then the role that analogue sampled-data systems playwithin the context of a general information processing environmentis examined and the required characteristics are identified.Trends in silicon integrated circuit processing technology aresummarised and their impact on sampled analogue circuits areidentified. Finally, the application of analogue current-modetechniques, and in particular switched-currents, to overcomesome of the limitations of previous voltage based approaches,is discussed.     

An ultra-low-power area-efficient non-volatile memory in a 0.18 μ m single-poly CMOS process for passive RFID tags

This paper presents an ultra-low-power area-efficient non-volatile memory(NVM) in a 0.18μm singlepoly standard CMOS process for passive radio frequency identification(RFID) tags.In the memory cell,a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore,the cell is designed with PMOS transistors and coupling capacitors to minimize its area.In order to improve its reliability,the cell consists of double floating gates to store the data,and the 1 kbit NVM was implemented in a 0.18μm single-poly standard CMOS process.The area of the memory cell and 1 kbit memory array is 96μm~2 and 0.12 mm~2,respectively.The measured results indicate that the program/erase voltage ranges from 5 to 6 V.The power consumption of the read/write operation is 0.19μW/0.69μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

This paper presents a 1Kb Sub-threshold SRAM in 180nm CMOS process based on a improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350mV, where the speed is 165KHz and the leakage power is 42nW and the dynamic power is less than 1uW. The designed SRAM can be used in ultra-low-power SoC.     

低功耗IR-UWB接收机和LNA设计研究

在分析各种超宽带(UWB)接收机系统结构的基础上,提出了一种低功耗IR-UWB接收机结构.该结构基于非相干通信机制,使用自混频技术和脉冲宽度调制方式(PPM).在该结构中,低噪声放大器(LNA)的低功耗优化是系统低功耗实现的关键.综合分析各种宽带LNA结构,提出了一种低功耗LNA设计.该LNA采用65 nmCMOS标准...     

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks(WBANs)in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver(RX)with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX)with fast lock-in PLL.A passive wake-up receiver(WuRx)for wake-up function with a high power conversion efficiency(PCE)CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm~2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.     

An ultra-low-power 1 kb sub-threshold SRAM in the 180 nm CMOS process

This paper presents a 1 kb sub-threshold SRAM in the 180 nm CMOS process based on an improved 11T SRAM cell with new structure. Final test results verify the function of the SRAM. The minimal operating voltage of the chip is 350 mV, where the speed is 165 kHz, the leakage power is 42 nW and the dynamic power is about 200 nW. The designed SRAM can be used in ultra-low-power SoC.     

Novel low-voltage ultra-low-power DVCC based on floating-gate folded cascode OTA

In this paper a novel low-voltage ultra-low-power differential voltage current conveyor (DVCC) based on folded cascode operational transconductance amplifier OTA with only one differential pairs floating-gate MOS transistor (FG-MOST) is presented. The main features of the proposed conveyor are: design simplicity; rail-to-rail input voltage swing capability at a low supply voltage of ±0.5 V; and ultra-low-power consumption of mere 10 μW. Thanks to these features, the proposed circuit could be successfully employed in a wide range of low-voltage ultra-low-power analog signal processing applications. Implementation of new multifunction frequency filter based on the proposed FG-DVCC is presented in this paper to take the advantages of the properties of the proposed circuit. PSpice simulation results using 0.18 μm CMOS technology are included as well to validate the functionality of the proposed circuit.     

An Ultra-low-power Area-efficient Non-volatile Memory in 0.18μm Single-poly CMOS Process

This paper presents an ultra-low-power area-efficient non-volatile memory (NVM) in a 0.18 μm single-poly standard CMOS process for passive radio frequency identification (RFID) tags. In the memory cell, a novel low-power operation method is proposed to realize bi-directional Fowler-Nordheim tunneling during write operation. Furthermore, the cell is designed with PMOS transistors and coupling capacitors to minimize its area. In order to improve its reliability, the cell consists of double floating gates to store the data, and the 1 kbit NVM was implemented in a 0.18 μm single-poly standard CMOS process. The area of the memory cell and 1 kbit memory array is 96 μm² and 0.12 mm², respectively. The measured results indicate that the program/erase voltage ranges from 5 to 6 V. The power consumption of the read/write operation is 0.19 μW/0.69 μW at a read/write rate of (268 kb/s)/(3.0 kb/s).     

一种用于医疗无线体域网的超低功耗射频收发机

本文提出了一种用于医疗无线体域网的2.4GHz频段超低功耗射频收发机,同时该收发机还带有900MHz频段辅助唤醒通信链路。根据无线体域网的非对称通信特点,我们提出了一种带有高能效非对称架构的射频收发机。该射频收发机包含一个带有超低功耗自由振荡环形振荡器的主接收机和带有快速锁定锁相环频率综合器的高速主发射机。我们还设计了一种带有高转换效率CMOS整流器的无源唤醒接收机,它使得传感器节点不仅具有按需工作的功能,同时还具有几乎为零的待机功耗。该芯片在0.18um CMOS工艺上实现,芯片核心面积为1.6mm2。主接收机在接收100Kbps数据率的OOK调制信号时,可以实现-55dBm的灵敏度;在1V电源电压下,仅消耗210uA电流。主发射机的发射功率为 3dBm,可以实现最大数据率为4Mbps/500Kbps/200Kbps的OOK/4FSK/2FSK调制,在1.8V电源电压下分别消耗3.25mA/6.5mA/6.5mA电流。无源唤醒接收机的最小可检测输入射频能量为-15dBm,整流器的转换效率大于25%