Adsp-21060的主机接口在实时图像处理中的应用

简要介绍了数字信号处理器Adsp 2 10 6 0和大规模可编程逻辑器件EP1K5 0。详细讨论了Adsp 2 10 6 0的主机接口工作模式以及一个实时图像跟踪处理器的硬件组成原理 ,在这个系统中EP1K5 0充当了主机。调试结果表明 ,所提出的硬件结构设计思想工作效率高 ,完全能够胜任实时图像处理的实际需要。     

2.4GHz动态CMOS分频器的设计

对现阶段的主流高速CMOS分频器进行分析和比较,在此基础上设计一种采用TSPC(truesingle phase clock)和E-TSPC(extended TSPC)技术的前置双模分频器电路.该分频器大大提高了工作频率,采用0.6μm CMOS工艺参数进行仿真的结果表明,在5V电源电压下,最高频率达到3GHz,功耗仅为8mW.     

逻辑分析仪在教学实验中的应用

硬件教学实验必须由验证性向设计性转变，才能达到培养学生设计能力和处理问题的能力。而逻辑分析仪是数字系统设计的常用工具．对于实验和教学都起着不可忽视的作用。     

理想九点五态控制器原理的叙述

用计算的方式叙述理想九点五态控制器的控制原理。为便于人们理解二阶对象的运动中控制的变化过程,将抽象的对象转换为人们熟知的L-R-C电路,通过调节输入电压(即控制作用)的大小和方向来实现对对象性能的调节,并使系统达到理想的性能指标。最后用仿真来验证计算结果的正确性。     

Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic

Currently there are design barriers inhibiting the implementation of high-precision digital signal processing (DSP) objects with field programmable logic (FPL) devices. This paper explores overcoming these barriers by fusing together the popular distributed arithmetic (DA) method with the residue number system (RNS) for use in FPL-centric designs. The new design paradigm is studied in the context of a high-performance filter bank and a discrete wavelet transform (DWT). The proposed design paradigm is facilitated by a new RNS accumulator structure based on a carry save adder (CSA). The reported methodology also introduces a polyphase filter structure that results in a reduced look-up table (LUT) budget. The 2C-DA and RNS-DA are compared, in the context of a FPL implementation strategy, using a discrete wavelet transform (DWT) filter bank as a common design theme. The results show that the RNS-DA, compared to a traditional 2C-DA design, enjoys a performance advantage that increases with precision (wordlength).     

双波长稳频CO_2激光模糊控制系统的建模与优化

报导一种模糊逻辑控制系统的建模与优化方法。以此方法设计的模糊逻辑控制器，用于双波长稳频ＣＯ２激光器的控制得到令人满意的结果。     

Cycle and circle tests of balance in gain graphs: Forbidden minors and their groups

We examine two criteria for balance of a gain graph, one based on binary cycles and one on circles. The graphs for which each criterion is valid depend on the set of allowed gain groups. The binary cycle test is invalid, except for forests, if any possible gain group has an element of odd order. Assuming all groups are allowed, or all abelian groups, or merely the cyclic group of order 3, we characterize, both constructively and by forbidden minors, the graphs for which the circle test is valid. It turns out that these three classes of groups have the same set of forbidden minors. The exact reason for the importance of the ternary cyclic group is not clear. © 2005 Wiley Periodicals, Inc. J Graph Theory     

A finite model property for RMImin

It is proved that the variety of relevant disjunction lattices has the finite embeddability property. It follows that Avron's relevance logic RMI _min has a strong form of the finite model property, so it has a solvable deducibility problem. This strengthens Avron's result that RMI _min is decidable. (© 2006 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

一阶形式系统K~*及其完备性

模糊命题演算的形式系统L＊已经在模糊逻辑与模糊推理的结合研究中得到了成功的应用.本文考虑与系统L＊相应的一阶逻辑理论,建立了一阶形式系统K＊,并证明了这个系统的完备性.