Dynamical analysis,circuit realization,and application in pseudorandom number generators of a fractional-order laser chaotic system

A new five-dimensional fractional-order laser chaotic system (FOLCS) is constructed by incorporating complex variables and fractional calculus into a Lorentz-Haken-type laser system. Dynamical behavior of the system, circuit realization and application in pseudorandom number generators are studied. Many types of multi-stable states are discovered in the system. Interestingly, there are two types of state transition phenomena in the system, one is the chaotic state degenerates to a periodical state, and the other is the intermittent chaotic oscillation. In addition, the complexity of the system when two parameters change simultaneously is measured by the spectral entropy algorithm. Moreover, a digital circuit is design and the chaotic oscillation behaviors of the system are verified on this circuit. Finally, a pseudo-random sequence generator is designed using the FOLCS, and the statistical characteristics of the generated pseudo-random sequence are tested with the NIST-800-22. This study enriches the research on the dynamics and applications of FOLCS.     

一种新型回路电阻测试仪的研究与设计

针对传统低压回路电阻测试仪只能在被测设备停电时使用的一大限制,本文提出并设计了一种新型低压回路电阻测试仪。该仪器可在低压设备运行状态下对其回路电阻进行测量,在保证测量精度的前提下减少了设备停电率,大大提高了工作效率。     

面向航空通信应用的边沿触发器教学设计

研究和分析了面向航空通信应用的边沿触发器教学设计。以边沿触发电路实现原理为核心,引导边沿触发机制的探究式学习；以航空机载网络通信为具体应用背景,引入科学研究和工程实现中实际问题,设计曼切斯特码检测系统实验；使得边沿触发器教学成为“知识再创造”的过程和创新实践的新载体,以期培养新工科背景下的独立、创新和实践精神。     

关于硬件木马电路检测技术分析及发展趋势探讨

本文结合HTH电路的复杂性等特征分析与实际应用现状,研究了HTH电路的具体检测技术方法并对当前热点技术进行对比分析,探讨了HTH电路检测方法的技术发展趋势。     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

一种智能型的PCB产业需求预测方法

目前需求预测在整个印制电路板产业的生产活动控制中正扮演着越来越重要的角色。分析了影响印制电路板需求的因素和现有的预测方法,提出了一种适用于PCB产业需求预测的有效方法——遗传/BP—神经网络。实验表明该方法能够进一步改善印制电路板预测的准确度和减少生产成本的消耗。     

宽带DDS跳频源设计

直接数字合成（DDS）简单可靠、控制方便，具有很高的频率分辨率，高速转换，非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后，提出宽带跳频源设计方案。     

一个基于PE分层技术的电子政务网络平台

电子政务网络建设的主要目标就是建立一个开放的、基于标准的统一网络平台，并在该平台上实现政府不同部门之间的信息交换和资源共享，同时保证各部门信息的独立和安全。通过介绍电子政务网络建设中的主流技术——MPLSVPN，提出了一种基于该技术原理的PE分层技术，详细讨论了基于该分层技术的电子政务网络平台的实现过程和主要技术，并对其性能参数进行了测试与分析。     

逻辑分析仪在教学实验中的应用

硬件教学实验必须由验证性向设计性转变，才能达到培养学生设计能力和处理问题的能力。而逻辑分析仪是数字系统设计的常用工具．对于实验和教学都起着不可忽视的作用。