Dielectric properties of beryllia ceramics in the near-millimeter wavelength range

We report the refractive indices and absorption coefficients for four beryllia (BeO) ceramic samples. These dielectric properties have been measured over the range from 4 to 18 cm^–1 by use of a Michelson interferometer. The index n, follows the linear relationship n=0.6517 cm³/g×+0.7130 with density, , over the range 2.8<<3.0 g/cm³.     

32位高速浮点乘法器优化设计

设计了一种用于频率为200 MHz的32位浮点数字信号处理器(DSP)中的高速乘法器.采用修正Booth算法与Wallace压缩树结合结构完成Carry Sum形式的部分积压缩,再由超前进位加法器求得乘积.对乘法器中的4-2压缩器进行了优化设计,压缩单元完成部分积压缩的时间仅为1.47 ns,乘法器延迟时间为3.5 ns.     

用EMODL实现的高速低功耗流水线乘法器

实现快速、低功耗以及节省面积的乘法器对高性能微处理器 (例如 DSP和 RISC)而言是至关重要的。文中详尽论述了新型的增强型多输出多米诺逻辑 ( EMODL)及其 n-MOS赋值树的尺寸优化方法 ,并用它实现了高速低功耗 2 0× 2 0 bit流水线乘法器。最后 ,通过 HSPICE仿真 ,确认了该乘法器结构的优越性 :流水线等待时间小 ( 2倍于系统时钟 )、运算速度高 ( 10 0 MOPS)以及低功耗 ( 2 3 .94m W)     

Cross-layer optimization for 3-D video transmission over cooperative relay systems

The rate budget constraint and the available instantaneous signal-to-noise ratio of the best relay selection in cooperative systems can dramatically impact the system performance and complexity of video applications, since they determine the video distortion. By taking into account these constrained factors, we first outline the signal model and formulate the system optimization problem. Next, we propose a new approach to cross-layer optimization for 3-D video transmission over cooperative relay systems. We propose procedures for estimation of the end-to-end instantaneous signal-to-noise ratio using an estimate of the available instantaneous signal-to-noise ratios between the source–destination, and source–relay–destination before starting to send the video signal to the best relay and destination. A novel approach using Lagrange multipliers is developed to solve the optimum bit allocation problem. Based on the rate budget constraint and the estimated the end-to-end instantaneous signal-to-noise ratio, the proposed joint source–channel coding (JSCC) algorithm simultaneously assigns source code rates for the application layer, the number of high and low priority packets for the network layer, and channel code rates for the physical layer based on criteria that maximize the quality of video, whilst minimizing the complexity of the system. Finally, we investigate the impact of the estimated the end-to-end instantaneous signal-to-noise ratio on the video system performance and complexity. Experimental results show that the proposed JSCC algorithm outperforms existing algorithms in terms of peak signal-to-noise ratio. Moreover, the proposed JSCC algorithm is found to be computationally more efficient since it can minimize the overall video distortion in a few iterations.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells

3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.     

一种低压高线性CMOS模拟乘法器设计

提出了一种新颖的CMOS四象限模拟乘法器电路．该乘法器基于交叉耦合平方电路结构,并采用减法电路来实现。它采用0．18μmCMOS工艺,使用HSPICE软件仿真。仿真结果显示,该乘法器电路在1．8V的电源电压下工作时,静态功耗可低至80μW,其线性输入范围达到±0．3V,-3dB带宽可达到1GHz,而且与先前低电压乘法器电路相比,在同样的功耗和电源电压下,具有更好的线性度。     

16×16位高速低功耗并行乘法器的实现

基于0.6μm双阱CMOS工艺模型,实现了一种高速低功耗16×16位并行乘法器。采用传输管逻辑设计电路结构,获得了低功耗的电路性能。采用改进的低功耗、快速Booth编码电路结构和4-2压缩器电路结构,它在2.5V工作电压下,运算时间达到7.18ns,平均功耗(100MHz)为9.45mW。     

一种可重构的高速流水线乘法器

本文针对在语音、视频等信号处理中出现的变速率信号处理,提出了一种新型的高速高效可重构流水线乘法器电路,并在0.25μm工艺条件下对电路进行了仿真.该电路通过控制流水级数处理变速信号,可有效地节约电路资源约34%,同时可保证频率达1.8GHz的高运算速度.     

电介质的频域特性与测量

从物质的分子结构基本模型出发，简要介绍了介电频域理论，提出了有关新的测量方法。