SFTMP——一个实现软件容错的多处理机系统

多版本软件通过设计相异性实现了软件容错。为了对这种方法进行研究，我们的课题实现了一个三版本软件系统，称之为SFTMP（SoftwareFault－TolerantMultiProcessor）。本文描述了SFTMP的硬件结构和软件执行支持环境，该环境包括同步、表决和监控功能、版本间的通讯及故障的恢复和重构。     

Self-reconfiguration of real-time communication in cyber-physical systems

Today, in domains like automation and robotics systems consist of various sensors and computation nodes. Due to the temporal dependency in quality of measured data, such Cyber-Physical Systems (CPS) commonly have real-time requirements on communication. In addition, these systems shall become more flexible and scalable, e.g., by adding new components to the CPS. This would be most suitable if a CPS could react to the presence of a new component and reconfigure itself to run afterward with the new component integrated to the CPS. This capability is covered by the term Plug-and-Produce. In this paper, we propose a concept to enable Plug-and-Produce within a CPS whose network uses different communication media, e.g., Ethernet and CAN. To enable real-time communication provided by different communication protocols, their different synchronization mechanisms have to be combined to get a common time base within the entire system. For this purpose, we consider Ethernet as well as CAN-based real-time communication protocols and their synchronization mechanisms. The proposed concept for self-reconfiguration aims to be integrated into our three layered software architecture that is presented as well.     

无人机自主编队飞行控制的技术问题

从未来无人机的性能需求出发,详细描述了无人机编队飞行的功能特点和核心技术。根据无人机的任务要求,将编队飞行分为作战编队、侦察编队和混合协同编队,同时研究了编队飞行控制的关键技术,并对无人机编队重构技术进行了探讨和分析。     

An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling

The paper proposes a novel heuristic technique for integrated hardware-software partitioning, hardware design space exploration and scheduling. The technique maps an application specified as a task graph on a heterogeneous architecture with an objective to minimize the latency of the task graph subject to the area constraint on the hardware coprocessor. The technique uses an iterative approach where the partitioner decides the processor mapping and HW design points of some tasks. The scheduler then simultaneously decides the processor mapping, HW design point and schedule time of the remaining tasks. There exists a tight coupling between the two design stages allowing them to produce superior quality designs in fewer iterations. The technique accounts for the time overheads due to inter-processor /intra-processor communication and shared memory access conflicts. It can therefore be used for both communication intensive and computation intensive applications. The technique also considers dynamic reconfiguration capability of the hardware coprocessor. The technique performs tradeoff analysis and maps hardware tasks to mutually exclusive temporal segments if this results in lower latency. The effectiveness of the technique is demonstrated by a case study of the JPEG image compression algorithm, comparison with an optimal ILP based approach and experimentation with synthetic graphs.     

一种基于Zynq-7000+AD9361的通用调制平台设计

针对一般调制平台互联性差、灵活性差、复用性差等问题,采用软硬件协同设计和部分动态可重配置等技术,设计了一种基于Zynq-7000和AD9361的通用调制平台。采用16APSK和QPSK的调制方式对通用调制平台的设计进行验证,其中平方根升余弦成形滤波器采用查找表形式的多相滤波器结构实现,该实现方法只用到加法运算。测试结果表明,在不同Zynq-7000开发板和不同调制方式下,替换部分硬件功能模块和修改软件配置,平台均能正常工作。与传统调制平台相比,本平台的设计以及功能实现具有灵活性强、复用性高等特点,具有广阔应用前景。     

网络虚拟化环境下基于预测的资源重配置算法

解决虚拟网动态加入、离开导致的底层网络资源占用不均衡问题,提出基于预测的资源重配置算法(FRRA)。FRRA用已知信息预测资源重配置时间间隔,代替已有算法中周期性时间间隔。采取两方面措施保证重配置时机全局最优:将资源划分为关键资源和普通资源并使用不同配置算法;根据资源迁移失败概率,推导重配置请求次数极限值。与算法VNA-II、PMPA实验比较表明,FRRA的重配置花费比VNA-II节省69%,比PMPA节省42%;FRRA的虚拟网请求接收率比VNA-II提高29%,比PMPA提高52%。     

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The divide and conquer technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(V^1/2) for the processor arrays considered in this paper, where V is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.     

Interprocedural Compiler Optimization for Partial Run-Time Reconfiguration

In this paper, we study the performance impact of dynamic hardware reconfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed hardware configuration instructions taking into account constraints such as the “FPGA-area placement conflicts” between the available hardware configurations. The presented algorithm allows the anticipation of hardware configuration instructions up to the application’s main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed hardware configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable hardware execution.     

基于SystemACE的FPGA全局动态可重配置的研究

FPGA的全局动态可重配置技术主要是指对运行中的FPGA器件的全部逻辑资源实现在系统的功能变换,从而实现硬件的时分复用。提出了一种基于systemACE的全局动态可重配置设计方法,首先介绍Xilinx SystemACE技术,详细分析FPGA的全局动态可重配置的原理,使用SystemACE控制器件和Compact Flash卡,并讨论了其中的若干细节,然后基于SystemACE实现了Virtex一5系列FPGA全局动态可重配置。实验结果表明,该方法稳定可靠,可实现8种不同比特流的动态配置,与传统的FPGA配置方法相比,其配置更灵活。     

DDS和可重组调制技术的原理和实现

可重组技术(Reconfiguration)是90年代出现的新技术．其基本思想是使用可反复重新组合连接方法的超大面积门阵列．靠软件加栽重新组合，实现功能可编程。对将直接数字频率合成技术(DDS)、可重组技术和数字信号处理技术应用于调制领域进行了研究，成功地实现FSK、MFSK(M=4)、MSK、PSK等调制。试验结果与理论分析逼近，调制的数字化程度高，具有很强的通用性和功能可重组性。