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1.
1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm2 is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm2 array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall Vmin of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances. 相似文献
2.
Dong‐Wook Kim 《ETRI Journal》2006,28(1):84-86
This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns. 相似文献
3.
范文跃 《信息安全与通信保密》2006,(8):66-68
在分析移动智能平台安全需求基础上,从逻辑原理、硬件组成、软件系统三个层面提出了移动智能平台的可信计算体系结构,之后提出了包含十种可信计算应用功能的全景图。 相似文献
4.
Kicheon Kim 《ETRI Journal》2006,28(1):31-44
In a packet switching network, congestion is unavoidable and affects the quality of real‐time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well‐known solutions for quality‐of‐service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network. 相似文献
5.
结合我国汽车计算平台工程,分析了国外相关的标准现状和基本框架,并为今后工作的开展提出了建议. 相似文献
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宽带DDS跳频源设计 总被引:1,自引:0,他引:1
直接数字合成(DDS)简单可靠、控制方便,具有很高的频率分辨率,高速转换,非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后,提出宽带跳频源设计方案。 相似文献
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多协议标记交换(MPLS)技术是综合利用网络第二层交换技术的有效性和第三层IP路由的灵活性等优点而产生的多层交换技术。通过在传统的IP包里加入标记,使路由转发依赖于标记,大大地提高IP包的转发速度,同时可使传统IP网络具有服务质量(QoS)能力。现主要分析MPLS体系结构,指出MPLS的一些应用。 相似文献
10.