Secure image encryption scheme using 4D-Hyperchaotic systems based reconfigurable pseudo-random number generator and S-Box

This paper introduces the design of a hardware efficient reconfigurable pseudorandom number generator (PRNG) using two different feedback controllers based four-dimensional (4D) hyperchaotic systems i.e. Hyperchaotic-1 and -2 to provide confidentiality for digital images. The parameter's value of these two hyperchaotic systems is set to be a specific value to get the benefits i.e. all the multiplications (except a few multiplications) are performed using hardwired shifting operations rather than the binary multiplications, which doesn't utilize any hardware resource. The ordinary differential equations (ODEs) of these two systems have been exploited to build a generic architecture that fits in a single architecture. The proposed architecture provides an opportunity to switch between two different 4D hyperchaotic systems depending on the required behavior. To ensure the security strength, that can be also used in the encryption process in which encrypt the input data up to two times successively, each time using a different PRNG configuration. The proposed reconfigurable PRNG has been designed using Verilog HDL, synthesized on the Xilinx tool using the Virtex-5 (XC5VLX50T) and Zynq (XC7Z045) FPGA, its analysis has been done using Matlab tool. It has been found that the proposed architecture of PRNG has the best hardware performance and good statistical properties as it passes all fifteen NIST statistical benchmark tests while it can operate at 79.101-MHz or 1898.424-Mbps and utilize only 0.036 %, 0.23 %, and 1.77 % from the Zynq (XC7Z045) FPGA's slice registers, slice LUTs, and DSP blocks respectively. Utilizing these PRNGs, we design two 16 × 16 substitution boxes (S-boxes). The proposed S-boxes fulfill the following criteria: Bijective, Balanced, Non-linearity, Dynamic Distance, Strict Avalanche Criterion (SAC) and BIC non-linearity criterion. To demonstrate these PRNGs and S-boxes, a new three different scheme of image encryption algorithms have been developed: a) Encryption using S-box-1, b) Encryption using S-box-2 and, c) Two times encryption using S-box-1 and S-box-2. To demonstrate that the proposed cryptosystem is highly secure, we perform the security analysis (in terms of the correlation coefficient, key space, NPCR, UACI, information entropy and image encryption quantitatively in terms of (MSE, PSNR and SSIM)).     

F-OFDM仿真系统设计与时频同步算法

针对新一代5G波形的F-OFDM技术开展了研究,通过把一个宽带分为若干个子带,对每个子带进行滤波处理以实现更好的通信效能。基于Simulink平台进行了F-OFDM仿真系统的搭建,重点对F-OFDM符号同步方法和频偏估计方法进行了研究与仿真分析。实验结果表明,基于Chu序列相比采用PN序列可以获得更好的同步效果,基于导频的Classen频偏估计算法相比基于CP的CFO估计算法和基于训练序列的Moose估计方法可以获得更好的频偏估计效果。     

Radial breathing-mode frequency of elastically confined spherical nanoparticles subjected to circumferential magnetic field

Knowledge of the vibrational properties of nanoparticles is of fundamental interest since it is a signature of their morphology, and it can be utilized to characterize their physical properties. In addition, the vibration characteristics of the nanoparticles coupled with surrounding media and subjected to magnetic field are of recent interest. This paper develops an analytical approach to study the radial breathing-mode frequency of elastically confined spherical nanoparticles subjected to magnetic field. Based on Maxwell's equations, the nonlocal differential equation of radial motion is derived in terms of radial displacement and Lorentz's force. Bessel functions are used to obtain a frequency equation. The model is justified by a good agreement between the results given by the present model and available experimental and atomic simulation data. Furthermore, the model is used to elucidate the effect of nanoparticle size, the magnetic field and the stiffness of the elastic medium on the radial breathing-mode frequencies of several nanoparticles. Our results reveal that the effects of the magnetic field and the elastic medium are significant for nanoparticle with small size.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

Handover and Uplink Power Control Performance in the 3.84 Mcps TDD mode of UTRA Network

In this article we consider the performance of the 3.84 Mcpstime-division duplex (TDD) mode of UTRA (Universal TerrestrialRadio Access) network. We emphasize two of the radio resourcemanagement algorithms, handover and uplink power control, whoserole in the overall system performance is studied extensively.First, a handover algorithm used in WCDMA (Wideband Code DivisionMultiple Access) standard is considered in a TDD-mode operation.This gives rise to a careful setting of different handoverparameters, and the evaluation of the effects to the systemperformance. Secondly, the specified uplink power controlalgorithm is considered. Since it is based on several user-mademeasurements which may involve both random and systematic errors acareful study about the suitability of the power control scheme iscarried out.     

基于压电陶瓷动态信息的结构裂纹识别方法

利用压电陶瓷的动态特性和压电系统的动态信息,对铝梁的裂纹损伤进行了分析研究。随着梁裂纹尺寸的增加,压电陶瓷片的导钠幅值下降,且系统固有频率减小。利用导钠幅值的变化和系统的动态信息,可以对裂纹的位置和尺寸大小进行识别。实验证明该方法的有效性。     

差分跳频通信系统的特点及性能

文章介绍了一种新型的短波跳频通信技术——差分跳频,分析了差分跳频技术区别于常规跳频技术的主要特点。针对按序列检测的信号接收方法,对差分跳频通信系统在AWGN信道下的性能进行了理论分析,同时做出相应的计算机仿真,证实了差分跳频通信技术和按序列检测方法的结合,使通信系统在AWGN信道下的性能得到了比较显著的提升。     

结构振动试验转接器的设计及安装问题

一些产品及其相关部件在作振动试验时，由于产品的外形或特殊要求不能直接安装在振动台面上，需要通过特别设计的转接器（夹具）来进行连接，这种夹具实际上是一种附加结构，它作为台面与试件之间的中介，如设置不当将影响振动试验结果的可靠性。本文通过对某事例的分析与研究，从试验频带、允许误差、跟随条件以及安装共振频率等方面阐明与讨论了相关夹具的特性、设计原则与安装等问题。     

OFDM系统中同步算法的FPGA 实现

给出了一种用于 OFDM 系统中可同时完成帧起始位置估计和载波频偏估计／补偿的同步算法及其 FPGA 实现方法。采用量化的方法对该不需要额外同步序列的估计算法进行了改进,提高了载波频偏的估计精度,并在数字域进行了频偏校正。在硬件实现上,利用 CORDIC 算法能够有效计算三角函数的特点,把频偏估计和频偏校正过程中的反正切运算和角度旋转操作转化成加法和移位操作,实现了计算精度、运算速度和硬件资源利用三方面性能的兼顾。