Design and implementation of a programming circuit in radiation-hardened FPGA

We present a novel programming circuit used in our radiation-hardened field programmable gate array （FPGA） chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory（SRAM）-based FPGA fabricated by a 0.5μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1×10⁵ rad（Si）,dose rate survivability of 1.5×10¹¹ rad（Si）/s and neutron fluence immunity of 1×10¹⁴ n/cm².     

抗辐射加固版图技术的性能比较

Total ionizing dose （TID） effect and single event effect （SEE） from space may cause serious effects on bulk silicon and silicon on insulator （SOl） devices, so designers must pay much attention to these bad effects to achieve better performance. This paper presents different radiation-hardened layout techniques to mitigate TID and SEE effect on bulk silicon and SOl device and their corresponding advantages and disadvantages are studied in detail. Under 0.13μm bulk silicon and SOl process technology, performance comparisons of two different kinds of DFF circuit are made, of which one kind is only hardened in layout （protection ring for bulk silicon DFF, T-gate for SO! DFF）, while the other kind is also hardened in schematic such as DICE structure. The result shows that static power and leakage of SOI DFF is lower than that of bulk silicon DFF, while SOI DFF with T-gate is a little slower than bulk silicon DFF with protection ring, which will provide useful guidance for radiation-hardened circuit and layout design.     

Design and performances of a low-noise and radiation-hardened readout ASIC for CdZnTe detectors

In this paper, we present the design and performances of a low-noise and radiation-hardened front-end readout application specific integrated circuit (ASIC) dedicated to CdZnTe detectors for a hard X-ray imager in space applications. The readout channel is comprised of a charge sensitive amplifier, a CR-RC shaping amplifier, an analog output buffer, a fast shaper, and a discriminator. An 8-channel prototype ASIC is designed and fabricated in TSMC 0.35-μm mixed-signal CMOS technology, the die size of the prototype chip is 2.2×2.2 mm². The input energy range is from 5 to 350 keV. For this 8-channel prototype ASIC, the measured electrical characteristics are as follows:the overall gain of the readout channel is 210 V/pC, the linearity error is less than 2%, the crosstalk is less than 0.36%, The equivalent noise charge of a typical channel is 52.9 e^- at zero farad plus 8.2 e^- per picofarad, and the power consumption is less than 2.4 mW/channel. Through the measurement together with a CdZnTe detector, the energy resolution is 5.9% at the 59.5-keV line under the irradiation of the radioactive source ²⁴¹Am. The radiation effect experiments show that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad(Si).     

一种抗辐射加固FPGA 编程电路的设计与实现

本文介绍了抗辐射加固SOI-SRAM基FPGA编程电路的设计与实现。该电路完成FPGA配置数据的下载与回读。该编程电路采用编程点直接寻址的方式,相对典型的移位寄存器链寻址方式不仅能够节约面积开销而且可以提供更为灵活的配置选择。通过对本电路提出的部分配置控制寄存器的配置,该编程电路可以实现的最小配置单元仅包含1位数据,FPGA更为灵活的部分重配置功能得以方便实现。层次化的仿真策略,对关键路径的优化及精密的版图布局保证了该电路的性能。此外对编程点进行了抗辐射加固设计。该电路在基于0.5μm部分耗尽SOI工艺SRAM基的FPGA中实现。功能测试结果表明, 该编程电路成功实现FPGA配置数据的下载与回读,且抗辐照实验结果表明,抗总剂量水平超过1x105Krad(Si), 抗瞬态剂量率水平超过1.5x1011 rad(Si)/s,抗中子注入量水平达到1x1014 n/cm2。     

Analysis of single event transient pulse-width in 65 nm commercial radiation-hardened logic cell

With the critical charge reduced to generate a single event effect (SEE) and high working frequency for a nanometer integrated circuit, the single event effect (SET) becomes increasingly serious for high performance SOC and DSP chips. To analyze the radiation-hardened method of SET for the nanometer integrated circuit, the n⁺ guard ring and p⁺ guard ring have been adopted in the layout for a 65 nm commercial radiation-hardened standard cell library. The weakest driving capacity inverter cell was used to evaluate the single event transient (SET) pulse-width distribution. We employed a dual-lane measurement circuit to get more accurate SET''s pulse-width. Six kinds of ions, which provide LETs of 12.5, 22.5, 32.5, 42, 63, and 79.5 MeV·cm²/mg, respectively, have been utilized to irradiate the SET test circuit in the Beijing Tandem Accelerator Nuclear Physics National Laboratory. The testing results reveal that the pulse-width of most SETs is shorter than 400 ps in the range of LET_eff from 12.5 MeV·cm²/mg to 79.5 MeV·cm²/mg and the pulse-width presents saturation tendency when the effective linear energy transfer (LET_eff) value is larger than 40 MeV·cm²/mg. The test results also show that the hardened commercial standard cell''s pulse-width concentrates on 33 to 264 ps, which decreases by 40% compared to the pulse-width of the 65 nm commercial unhardened standard cell.     

A radiation-hardened SOl-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute.The new logic cell （LC）,with a multi-mode based on 3-input look-up-table（LUT）,increases logic density about 12%compared to a traditional 4-input LUT.The logic block（LB）,consisting of 2 LCs,can be used in two functional modes:LUT mode and distributed read access memory mode.The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource.The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs,112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming.The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly.Moreover,the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad（Si）,a dose rate survivability of 1.5×10¹¹rad（Si）/s and a neutron fluence immunity of 1×10¹⁴ n/cm².     

辐射加固SOI的SRAM基FPGA中IO模块阵列的设计与实现

本文中我们提出了一个用于辐射加固的SRAM基FPGA VS100的输入输出模块阵列,该FPGA用0.5微米部分耗尽SOI工艺设计,在中电集团58所流片。与FPGA的特性一致,每一个IO单元都由布线资源和两个IOC组成,IOC包括信号通路电路,可编程输入/输出驱动器和ESD保护网络组成。IO模块能用于不同的工作模式时,边界扫描电路既可以插入在输入输出数据路径电路和驱动器之间,也可以作为透明电路。可编程IO驱动器使IO模块能够用于TTL和CMOS电平标准。布线资源使得IO模块和内部逻辑之间的连接更加灵活和方便。辐射加固设计,包括A型体接触晶体管,H型体接触晶体管和特殊的D触发器的设计提高了抗辐射性能。ESD保护网络为端口上的高脉冲提供了放电路径,防止大电流损坏内部逻辑。这些设计方法可以适用于不同大小和结构的FPGA设计。IO单元阵列的功能和性能经过了功能测试和辐射测试的考验,辐照实验结果表明,抗总剂量水平超过100Krad(Si), 抗瞬态剂量率水平超过1.510¹¹rad(Si)/s,抗中子注入量水平达到110¹⁴ n/cm²。     

抗辐射SOI器件栅氧可靠性研究

对抗辐射SOI器件栅氧可靠性进行研究,比较了体硅器件、SOI器件、抗总剂量加固SOI器件的栅氧可靠性,发现SOI材料片的制备与抗总剂量加固过程中的离子注入工艺都会对顶层硅膜造成影响,进而影响栅氧可靠性。最后通过恒压应力法表征栅氧介质随时间击穿(TDDB)的可靠性,结果显示抗总剂量辐射加固工艺的12.5 nm栅氧在125℃高温5.5 V工作电压下TDDB寿命达到14.65年,满足SOI抗总剂量辐射加固工艺对栅氧可靠性的需求。     

基于SOI的抗辐射加固FPGA芯片

介绍抗辐射VS1000 FPGA芯片架构及其设计实现。改进的基于3输入查找表的多模式逻辑单元,与传统的基于4输入查找表相比,可以提高约12%的逻辑利用率。逻辑模块由两个逻辑单元组成,可以被配置成两种工作模式：LUT模式和分布式RAM模式。新颖的层次化布线通道模块和开关模块可以极大的提高布线资源的布通率。VS1000芯片包括392个可编程逻辑单元,112个用户IO以及与IEEE 1149.1兼容的边界扫描逻辑,采用0.5 um部分耗尽绝缘体上硅CMOS工艺全定制设计并流片。功能测试结果表明, 芯片软硬件能够成功配合且实现用户特定功能。抗辐照实验结果表明,抗总剂量水平超过100Krad(Si), 抗瞬态剂量率水平超过1.510¹¹rad(Si)/s,抗中子注入量水平达到110¹⁴ n/cm²。     

功率集成电路TID加固环栅器件研究现状综述

总结了标准工艺下功率集成电路中总剂量辐射(TID)加固环栅MOS器件与环栅功率器件的研究现状,归纳了不同结构形态的环栅器件的性能优劣,推荐8字形环栅MOS器件、华夫饼功率器件及回字形LDMOS器件结构用于功率集成电路的TID加固设计。同时,阐述了现有环栅MOS器件等效W/L的建模情况,提出保角变换是环栅MOS器件等效W/L精确建模的重要方法,最后还给出了环栅器件建库的基本流程。