Process optimization of polymetal (W/WN/Polysilicon) gate and its impact on dynamic random-access memory chip performance in 0.14-µm technology

This paper summarizes the problems and solutions in the process integration and device and circuit performances of fully working, 256-megabit, dynamic random-access memory (DRAM) chips employing poly-metal gate. In the circuit analysis, an anomalous decay of the electrical signal was observed as the signal proceeds through the delays. A circuit simulation suggested the presence of parasitic components in the gate tungsten/polysilicon interface. The experiments on the tungsten-electrode formation and metal-to-gate contact formation schemes confirmed the effects of the parasitic components when the scheme employing an in-situ formation of diffusion barrier is used. The search for a new cleaning chemical for the postgate etch process was also considered in the integration because it was found to significantly affect the data-retention characteristics. Finally, the temperature dependence of the data retention of the chips employing polymetal- and polycide-gates demonstrated the results to be quite comparable to each other.     

Work function measurement of tungsten polycide gate structures

Three MOS gate structures; polysilicon, tungsten silicide and tungsten polycide, were fabricated and their workfunctions measured with the high frequency C-V technique. The work functions were 4.14 ev and 4.82 ev for phosphorus doped polysilicon and silicon-rich tungsten silicide, respectively. The tungsten polycide structure, however, showed a variance between 4.14 ev and 4.38 ev for different experiments. The polycide MOS device threshold was about 0.15 volt higher than that of polysilicon. Phosphorus out-diffusion and tungsten diffusion along polysilicon grain boundaries were postulated to explain this phenomenon.     

WSI Polycide工艺的研究

文章基于0.5μm CMOS工艺,研究了造成Polycide工艺中WSI剥落、色斑等异常现象的原因。同时,研究了WSI淀积前清洗、退火温度及Cap Layer层对WSI薄膜翘曲度及应力的影响,并通过实验优化,以大量的数据为依据,对影响WSI薄膜特性的工艺参数进行调试和论证,主要考察更改各条件对圆片翘曲度及应力的变化,并通过显微镜镜检圆片表面,获得了0.5μm Polycide工艺较优的工艺条件。实验结果表明,在WSI淀积后增加Cap Layer层工艺对Polycide工艺工期WSI剥落、色斑等异常有较好的改善作用,且圆片表面形貌能达到MOS器件的工艺制造要求。