SDN中基于KMOBPSO的高可靠性控制器部署算法

针对SDN中控制器系统的单节点故障问题,兼顾系统成本和系统时延,应用N+1冗余备份模型来提高SDN控制器部署的可靠性,并将其抽象为多目标优化问题.同时,提出了一种融合K-means聚类算法和遗传算子的多目标二进制粒子群算法——KMOBPSO算法,以求解SDN控制器高可靠性部署问题的解.仿真结果表明,所提算法具有求解精度高、分布均匀、沿Pareto前沿面覆盖广的特点,能够显著提高SDN中控制器部署的可靠性.     

Logarithmic Regge pole

This work presents the subtraction procedure and the Regge cut in the logarithmic Regge pole approach. The subtraction mechanism leads to the same asymptotic behavior as previously obtained in the non-subtraction case. The Regge cut, in contrast, introduces a clear role to the non-leading contributions for the asymptotic behavior of the total cross-section. From these results, some simple parameterization is introduced to fit the experimental data for the proton-proton and antiproton-proton total cross-section above some minimum value up to the cosmic-ray. The fit parameters obtained are used to present predictions for the \begin{document}$ \rho(s)$\end{document} -parameter as well as to the elastic slope \begin{document}$ B(s)$\end{document} at high energies.     

贴片设备的选择

随着电子工业的飞速发展,贴片设备已被广泛应用于大规模电子组装生产上。文章就贴片机选型时应注意的几个关键技术问题作简单介绍,希望对企业选择贴装设备有一定的帮助。     

A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants

This paper introduces a methodology for symbolic pole/zero extraction based on the formulation of the time-constant matrix of the circuits. This methodology incorporates approximation techniques specifically devoted to achieve an optimum trade-off between accuracy and complexity of the symbolic root expressions. The capability to efficiently handle even large circuits will be demonstrated through several practical circuits.     

Geometric quadrisection in linear time, with application to VLSI placement

We consider the following problem: given a set of points in the plane, each with a weight, and capacities of the four quadrants, assign each point to one of the quadrants such that the total weight of points assigned to a quadrant does not exceed its capacity, and the total distance is minimized.

This problem is most important in placement of VLSI circuits and is likely to have other applications. It is NP-hard, but the fractional relaxation always has an optimal solution which is “almost” integral. Hence for large instances, it suffices to solve the fractional relaxation. The main result of this paper is a linear-time algorithm for this relaxation. It is based on a structure theorem describing optimal solutions by so-called “American maps” and makes sophisticated use of binary search techniques and weighted median computations.

This algorithm is a main subroutine of a VLSI placement tool that is used for the design of many of the most complex chips.     

LED生产过程中的质量控制

对LED封装过程可能出现的问题逐一指出，并提出解决的办法，着重介绍封装位置对LED发光亮度的影响。以期引起LED封装管理人员及工作人员的注意。     

薄膜磁头磁轭制备工艺研究

本文重点讨论了用不同的工艺方法来制备薄膜磁头中的关键元件-磁轭。采用多次光刻的方法克服湿法工艺中磁性膜NiFe层的侧向钻蚀问题，从而实现对磁轭几何尺寸的精确控制，并对几种工艺方法的优缺点作了比较详细的分析。     

电流模式n阶传输函数的OA-OTA实现

提出了一种新的实现任意 n阶电流模式传输函数的网络结构。该电路仅含运算放大器 (OA)和运算跨导放大器 (OTA)有源器件 ,因而适于全集成。适当设置 OTA的跨导值能实现任意高阶传输函数 ,且传输函数的系数可独立调整。文中推导了滤波器的设计公式 ,并给出了截止频率为 1 0 0 k Hz的三阶巴特沃斯低通滤波器实例 ,PSPICE仿真结果表明所提电路及设计公式是正确的     

The asymptotic behavior of queueing systems: Large deviations theory and dominant pole approximation

This paper presents the exact asymptotics of the steady state behavior of a broad class of single-node queueing systems. First we show that the asymptotic probability functions derived using large deviations theory are consistent (in a certain sense) with the result using dominant pole approximations. Then we present an exact asymptotic formula for the cumulative probability function of the queue occupancy and relate it to the cell loss ratio, an important performance measure for service systems such as ATM networks. The analysis relies on a new generalization of the Taylor coefficients of a complex function which we call characteristic coefficients. Finally we apply our framework to obtain new results for the M/D/1 system and for a more intricate multiclass M/D/n system.     

Preprocessing of rotamers for protein design calculations

We have developed a process that significantly reduces the number of rotamers in computational protein design calculations. This process, which we call Vegas, results in dramatic computational performance increases when used with algorithms based on the dead-end elimination (DEE) theorem. Vegas estimates the energy of each rotamer at each position by fixing each rotamer in turn and utilizing various search algorithms to optimize the remaining positions. Algorithms used for this context specific optimization can include Monte Carlo, self-consistent mean field, and the evaluation of an expression that generates a lower bound energy for the fixed rotamer. Rotamers with energies above a user-defined cutoff value are eliminated. We found that using Vegas to preprocess rotamers significantly reduced the calculation time of subsequent DEE-based algorithms while retaining the global minimum energy conformation. For a full boundary design of a 51 amino acid fragment of engrailed homeodomain, the total calculation time was reduced by 12-fold.