Full counting statistics of transport electrons through a two-level quantum dot with spin–orbit coupling

We study the full counting statistics of transport electrons through a semiconductor two-level quantum dot with Rashba spin–orbit (SO) coupling, which acts as a nonabelian gauge field and thus induces the electron transition between two levels along with the spin flip. By means of the quantum master equation approach, shot noise and skewness are obtained at finite temperature with two-body Coulomb interaction. We particularly demonstrate the crucial effect of SO coupling on the super-Poissonian fluctuation of transport electrons, in terms of which the SO coupling can be probed by the zero-frequency cumulants. While the charge currents are not sensitive to the SO coupling.     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

有线电视系统干扰信号的产生及排除

通过对有线电视系统干扰信号产生原因的理论分析，提出在实际操作中的解决方案，以期达到使有线电视系统信号的输出更稳定、电视画面更清晰的目的。     

智能化中高压变频器实载试验平台的实现

中、高压变频器产量越来越多，但试验手段大多比较落后，一般采用带电机空转的方法。本文介绍了一个高压变频器试验平台，通过该平台可以对电压等级在3kV～10kV、功率在5000kW以下的变频器进行实载试验。     

超高压大容量铝电解电容器的研制

分析了大功率设备用超高压大容量铝电解电容器的特点,通过研制工作电解液、制订制作工艺及零部件设计方案,研制出的超高压大容量铝电解电容器具有损耗角正切小(tgδ为0.25)、承受纹波电流能力强(100 Hz,2.12～27.8 A)及寿命长的特点,耐久性达到85℃,5 000 h。     

一种基于混沌同步的噪音衰减算法

论文提出了一种混沌通信系统的噪音衰减算法,该算法利用混沌同步现象在接收端获得正确的噪音估计值,从而从接收信号中滤除噪音恢复出正确的信号。通过数值仿真试验表明该方法是可行的。