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1.
宽带DDS跳频源设计 总被引:1,自引:0,他引:1
直接数字合成(DDS)简单可靠、控制方便,具有很高的频率分辨率,高速转换,非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后,提出宽带跳频源设计方案。 相似文献
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介绍了医用红宝石激光器触摸屏控制系统的基本结构,分析了医用红宝石激光器中主要电磁干扰(EMI)的产生机制,提出了具体的电磁兼容(EMC)技术措施并得到实验验证。 相似文献
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介绍了单端正向变换器基本电路,重点叙述带三路调节DC电压的100KHZ180W离线电源。它采用具有低导电阻RDS和低栅极电荷Qg的新型场效应管(QFET)作为变换电路的主开关器件,降低了电源开关损耗并提高了效率3%-5%。 相似文献
5.
This article introduces the basic structure of a symmetric self-electrooptic effect device (S-SEED), and applies the Kirchoff' s current law and a purely equivalent capacitive model, to analyze S-SEED's switch characteristics. Linear approximation and N-segment approximation are utilized to obtain S-SEED's voltage-time (V-T) and characteristics. Theoretical analysis is verified by simulations, and the results demonstrate that the precision of S-SEED's switch time can satisfy the requirement in applications with linear approximation. Moreover, the simulations compare S-SEED's switch characteristics with different input powers and input contrast ratios, which reveal that increasing input contrast ratio is an effective way to improve S-SEED's switch characteristics. 相似文献
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We carried out detailed calculations for photorefractive wave-mixing switches based on one of three crystals with high electro-optic coefficients, namely, BaTiO3, Strontium Barium Niobate (SBN (0.75)), and Potasium Sodium Strontium Barium Niobate (KNSBN). A comparison of results for the three crystals shows that a 0_-cut BaTiO3 crystal is suitable for a longitudinal switch and requires a voltage of about 80 for a 2-mm-thick crystal to induce sufficient phase mismatch. The electrodes must be transparent for the incident and diffracted beams. A 45_-cut SBN (0.75) crystal, however, is suitable for a lateral switch and requires a voltage of about 150 for a 1-mm-wide crystal. The electrodes do not need to be transparent. 相似文献
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Yuji Oie Tatsuya Suda Masayuki Murata Hideo Miyahara 《International Journal of Satellite Communications and Networking》1991,9(5):285-303
One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (asynchronous transfer mode). ATM can be characterized by very high speed transmission links and simple, hard-wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks. A number of designs have been proposed for implementing ATM switches. Although many differences exist among the proposals, the vast majority of them are based on self-routeing multistage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routeing capability and suitability for VLSI implementation. Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques have also been proposed to improve the performance of blocking and non-blocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues. 相似文献
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Broadband packet networks based on asynchronous transfer mode (ATM) are expected to provide a wide range of services, including motion video, voice, data and image. When these networks become prevalent, some applications such as motion video and high-speed LAN interconnections will place a very large bit rate requirement on the channels. Currently, the physical layer supported by the synchronous optical network (SONET) allows the transmission of up to 2.4 Gbit/s with the OC-48 optical interface. However, it is not feasible for the electronic packet switch to route packets at this rate on a single link. In this paper we present a design of a broadband packet switch that uses multiple links in parallel to realize a high-speed channel. This implementation permits the switch to operate at the lower link rate, which can be at 150 Mbit/s, while having the ability to support a virtual circuit at a higher rate (up to 2.4 Gbit/s). The main contribution of the design is that packet sequence on a channel is still maintained even though packets are allowed to use any of the links belonging to the same channel. Besides allowing the switch to function at a slower rate than the transmission channel rate, the implementation of the multilinks benefits from statistical multiplexing gain. Analytical results show the performance advantages of multilink design with respect to delay, throughput and packet loss probability. 相似文献