Stress analysis of Si1−xGex embedded source/drain junctions

The purpose of this paper is to evaluate the impact of the geometry of embedded Si_1−xGe_x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si_1−xGe_x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.     

GeOI pMOSFETs空穴迁移率的物理模型

A physical model of hole mobility for germanium-on-insulator p MOSFETs is built by analyzing all kinds of scattering mechanisms, and a good agreement of the simulated results with the experimental data is achieved, confirming the validity of this model. The scattering mechanisms involved in this model include acoustic phonon scattering, ionized impurity scattering, surface roughness scattering, coulomb scattering and the scattering caused by Ge film thickness fluctuation. The simulated results show that the coulomb scattering from the interface charges is responsible for the hole mobility degradation in the low-field regime and the surface roughness scattering limits the hole mobility in the high-field regime. In addition, the effects of some factors, e.g. temperature, doping concentration of the channel and the thickness of Ge film, on degradation of the mobility are also discussed using the model, thus obtaining a reasonable range of the relevant parameters.     

Characterization of device performance and reliability of high performance Ge-on-Si field-effect transistor

Analyzed herein is the impact of Si interface passivation layer (IPL) on device performance and reliability of Ge-on-Si field-effect transistors with HfSiO/TaN gate stack. Silicon passivation technique reduced the interface trap density as well as the bulk trap density. Lower trap density obtained with Si IPL improved charge trapping characteristics and reliability under constant voltage stress. NBTI characteristics obtained with Si IPL and without Si IPL proved that Si passivation was very effective to suppress the interface/bulk trap densities and improved transport characteristics of Ge MOSFETs.     

Ge metal oxide semiconductor field effect transistors with optimized Si cap and HfSiO2 high-k metal gate stacks

High mobility metal-oxide-semiconductor-field-effect-transistors (MOSFETs) are demonstrated on high quality epitaxial Si_0.75Ge_0.25 films selectively grown on Si (100) substrates. With a Si cap processed on Si_0.75Ge_0.25 channels, HfSiO₂ high-k gate dielectrics exhibited low C–V hysteresis (<10 mV), interface trap density (7.5 × 10¹⁰), and gate leakage current (∼10⁻²A/cm² at an EOT of 13.4 Å), which are comparable to gate stack on Si channels. The mobility enhancement afforded intrinsically by the Si_0.75Ge_0.25 channel (60%) is further increased by a Si cap (40%) process, resulting in a combined ∼100% enhancement over Si channels. The Si cap process also mitigates the low potential barrier issues of Si_0.75Ge_0.25 channels, which are major causes of the high off-state current of small band gap energy Si_0.75Ge_0.25 pMOSFETs, by improving gate control over the channel.     

90nm pMOSFETs NBTI退化模型及相关机理

对90nm pMOSFETs在不同温度及栅压应力下的NBTI效应进行了研究,从而提出了90nm pMOSFETs NBTI退化对时间t、温度T及栅压应力Vg的模型.时间模型及温度模型与过去研究所提出的模型相似,但是关键参数有所改变.栅压应力模型遵循双对数关系,这与传统的单对数栅压应力模型不同.将较低的栅压应力也考虑在内时,双对数栅压应力模型较单对数栅压应力模型更为准确.     

90nm pMOSFETs NBTI退化模型及相关机理

对90nm pMOSFETs在不同温度及栅压应力下的NBTI效应进行了研究,从而提出了90nm pMOSFETs NBTI退化对时间t、温度T及栅压应力Vg的模型.时间模型及温度模型与过去研究所提出的模型相似,但是关键参数有所改变.栅压应力模型遵循双对数关系,这与传统的单对数栅压应力模型不同.将较低的栅压应力也考虑在内时,双对数栅压应力模型较单对数栅压应力模型更为准确.     

Hot carrier degradation and a new lifetime prediction model in ultra-deep sub-micron pMOSFET

The hot carrier effect (HCE) of an ultra-deep sub-micron p-channel metal-oxide semiconductor field-effect transistor (pMOSFET) is investigated in this paper. Experiments indicate that the generation of positively charged interface states is the predominant mechanism in the case of the ultra-deep sub-micron pMOSFET. The relation of the pMOSFET hot carrier degradation to stress time (t), channel width (W ), channel length (L), and stress voltage (Vd ) is then discussed. Based on the relation, a lifetime prediction model is proposed, which can predict the lifetime of the ultra-deep sub-micron pMOSFET accurately and reflect the influence of the factors on hot carrier degradation directly.     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.