Discrete Wavelet Transform: Architectures, Design and Performance Issues

Due to the demand for real time wavelet processors in applications such as video compression [1], Internet communications compression [2], object recognition [3], and numerical analysis, many architectures for the Discrete Wavelet Transform (DWT) systems have been proposed. This paper surveys the different approaches to designing DWT architectures. The types of architectures depend on whether the application is 1-D, 2-D, or 3-D, as well as the style of architecture: systolic, semi-systolic, folded, digit-serial, etc. This paper presents an overview and evaluation of the architectures based on the criteria of latency, control, area, memory, and number of multipliers and adders. This paper will give the reader an indication of the advantages and disadvantages of each design.     

MPP中确定临界处理器数的方法

本文提出了并行求解问题时所应征用ＭＰＰ系统中临界处理器数的选择方法，该方法根据问题图中每一结点的时间特征进行选择，可操作性好，易于实现，特别适用于基于互连网络的ＭＰＰ系统和分布式系统。     

Heuristic Algorithms and Scatter Search for the Cardinality Constrained P||Cmax Problem

We consider the generalization of the classical P||C_max problem (assign n jobs to m identical parallel processors by minimizing the makespan) arising when the number of jobs that can be assigned to each processor cannot exceed a given integer k. The problem is strongly NP-hard for any fixed k > 2. We briefly survey lower and upper bounds from the literature. We introduce greedy heuristics, local search and a scatter search approach. The effectiveness of these approaches is evaluated through extensive computational comparison with a depth-first branch-and-bound algorithm that includes new lower bounds and dominance criteria.     

A Tandem Queue with Coupled Processors: Computational Issues

In Resing and Örmeci [16] it is shown that the two-stage tandem queue with coupled processors can be solved using the theory of boundary value problems. In this paper we consider the issues that arise when calculating performance measures like the mean queue length and the fraction of time a station is empty. It is assumed that jobs arrive at the first station according to a Poisson process and require service at both stations before leaving the system. The amount of work that a job requires at each of the stations is an independent, exponentially distributed random variable. When both stations are nonempty, the total service capacity is shared among the stations according to fixed proportions. When one of the stations becomes empty, the total service capacity is given to the nonempty station. We study the two-dimensional Markov process representing the numbers of jobs at the two stations. The problem of finding the generating function of the stationary distribution can be reduced to two different Riemann-Hilbert boundary value problems, where both problems yield a complete analytical solution. We discuss the similarities and differences between the two problems, and relate them to the computational aspects of obtaining performance measures.     

多核处理器中任务调度与负载均衡的研究

针对多核处理器系统的特点,对任务分配及调度模型进行改进,提高各处理器相对均衡负载度,并在此基础上提出一种均衡种群遗传算法（BPGA）．算法在任务节点的高度约束条件下,达到任务节点在处理核上随机分配,而任务节点数均衡分配．采用随机生成图法进行模拟实验,与其他算法相比,BPGA算法有更小的调度长度和较少的执行时间．     

Architectural and Basic Circuit Considerations for a Flexible 128 × 128 Mixed-Signal SIMD Vision Chip

From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35 m standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (7 bits) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330 GOPs (Giga Operations per second), and uses the power supply (180 GOP/Joule) and the silicon area (3.8 GOPS/mm²) efficiently, and is able to maintain VGA processing throughputs of 100 Frames/s with about 10–20 basic image processing tasks on each frame.     

Mixed parallel processors with interdependent blocking

This paper studies a system of parallel service facilities or processors with mixed exponential and non-exponential queues, a non-exponential finite source input and interdependent arrival as well as departure blocking such as due to a common pool or shared resource. A concrete invariance condition upon the blocking protocol is provided. Under this condition the stationary busy source distribution is shown to be of an insensitive product form. The result unifies and extends known product form results as will be illustrated by several examples.     

TMS 32020单片信号处理器在测控系统中的应用

在卫星地面测控系统中,要求在低信噪比(如-20分贝)条件下提取目标的多普勒频率信息,以引导接收机锁相环捕获信号并锁定。模拟式频率引导采用经典的晶体滤波器组,其数量大、成本高、重量体积大。数字式频率引导采用对接收信号采样序列进行FFT运算处理实现对目标的频率捕获,具有显著的优越性。作者等人以8086微机实现的数字频率引导设备已成功地应用于同步通讯卫星测控站中。为了进一步提高处理速度,采用了TMS32020单片信号处理器研制出频率引导快速处理机,使频率引导处理时间提高15倍以上。该成果的硬件设备可适应不同的实时数字信号处理要求,应用于雷达、通讯、遥控、仪器、语音、智能等各种场合。     

Minimizing the total weighted late work in scheduling of identical parallel processors with communication delays

This paper addresses a certain type of scheduling problem that arises when a parallel computation is to be executed on a set of identical parallel processors. It is assumed that if two precedence-related tasks are processed on two different processors, due to the information transferring, there will be a task-dependent communication delay between them. For each task, a processing time, a due date and a weight is given while the goal is to minimize the total weighted late work. An integer linear mathematical programming model and a branch-and-bound algorithm have been developed for the proposed problem. Comparing the results obtained by the proposed branch-and-bound algorithm with those obtained by CPLEX, indicates the effectiveness of the method.     

Minimizing the number of machines for minimum length schedules

In this paper, we present a new objective function for scheduling on parallel machines: minimizing the number of machines for schedules of minimum length. We study its complexity and we prove the NP-completeness of this problem, even if there is no precedences or for unitary execution times. We propose several polynomial algorithms for various particular cases.