Optical Diffractive Memories: Angular Selectivity and Diffraction Efficiency in Dichromated Gelatin

Two thousand images of resolution 512×512 pixels as a regular matrix pattern of 10×10 elements are stored, where each element is angularly multiplexed 20 times in a 25 μm thickness of dichromated gelatin emulsion without cross-talk effect. The surface area of the matrix is 1 cm². We show good concordance of the angular selectivity between the experimental result and theory. The diffraction efficiency of each 20 multiplexed images is measured and has nearly the same value. Examples of reconstructed images for multiple applications are given, for example, storage of 160,000 images on a 3′1/2 floppy disc format, which is about 100 min of black and white film. Application can be made to automobile cartography and storage of X-ray images as well as weather forecast images. Colored diffractive images are also possible and are illustrated.     

Formation of C49-TiSi2 in flash memories: a nucleation controlled phenomenon?

The formation of Ti silicides has been examined in flash memories with 0.25 μm linewidth by X-ray diffraction, scanning electron microscopy, and transmission electron microscopy. It has been observed that, after the first rapid thermal process and the selective metal etch, there is no silicide on the source and on a majority of drain contacts while C49-TiSi₂ is found on the gate. A pre-amorphisation implant increases drastically the formation of C49-TiSi₂ in the drain zone while modifications of annealing conditions have little impact. These results indicate that the formation of C49-TiSi₂ is most likely controlled by nucleation and that this nucleation is sensitive to both the width and the length of the reaction zone. The formation of a Ti rich silicide may play an important role in this nucleation by decreasing the driving force for the formation of C49-TiSi₂. Curiously enough, the formation of C49-TiSi₂ appears thus as a major concern for the salicide process in flash memories.     

Multistate/multifunctional behaviour of 4'-hydroxy-6-nitroflavylium: a write-lock/read/unlock/enable-erase/erase cycle driven by light and pH stimulation

We have investigated the network of reactions observed for the photochromic 4'-hydroxy-6-nitroflavylium compound in aqueous solutions upon pH changes (including pH jump and stopped flow experiments) and light excitation. The changes observed in the NMR and UV/Vis spectra allowed identification of ten different forms in which this compound can be transformed depending on the experimental conditions. Equilibrium and kinetic constants have been determined. Compared with other members of the flavylium family, 4'-hydroxy-6-nitroflavylium is characterized by a large cis-->trans isomerization barrier, and a very efficient hydration reaction. These peculiar features allow writing, reading, storing and erasing photonic information on 4'-hydroxy-6-nitroflavylium by a novel cyclic process that involves the following steps: write-lock/read/unlock/enable-erase/erase.     

一种用于16位流水线ADC的多比特子DAC电容失配校准方法

多比特子DAC的电容失配误差在流水线AIX:输出中引入非线性误差,不仅严重降低AEK、转换精腰.而且通常的校准技术无法对非线性误差进行校准.针对这种情况,本文提出了一种用于16位流水线ADC的多比特子DAC电容失配校准方法.该设计误差提取方案在流片后测试得到电容失配误差.进而计算不同输入情况下电容失配导致的MDAC输出误差,根据后级的误差补偿电路将误差转换为卡乏准码并存储在芯片中,对电容失配导致的流水级输出误差进行校准.仿真结果表明.卡《准后信噪失真比SINAD为93.34 dB.无杂散动态范围SFDR为117.86 dB,有效精度EN()B从12.63 bit提高到15.26 bit.     

Characterization of Cr‐doped Sb2Te3 films and their application to phase‐change memory

Phase‐change memory (PCM) is regarded as one of the most promising candidates for the next‐generation nonvolatile memory. Its storage medium, phase‐change material, has attracted continuous exploration. Along the traditional GeTe–Sb₂Te₃ tie line, the binary compound Sb₂Te₃ is a high‐speed phase‐change material matrix. However, the low crystallization temperature prevents its practical application in PCM. Here, Cr is doped into Sb₂Te₃, called Cr–Sb₂Te₃ (CST), to improve the thermal stability. We find that, with increase of the Cr concentration, grains are obviously refined. However, all the CST films exhibit a single hexagonal phase as Sb₂Te₃ without phase separation. Also, the Cr helps to inhibit oxidation of Sb atoms. For the selected film CST_10.5, the resistance ratio between amorphous and crystalline states is more than two orders of magnitude; the temperature for 10‐year data retention is 120.8 °C, which indicates better thermal stability than GST and pure Sb₂Te₃. PCM cells based on CST_10.5 present small threshold current/voltage (4 μA/0.67 V). In addition, the cell can be operated by a low SET/RESET voltage pulse (1.1 V/2.4 V) with 50 ns width. Thus, Cr–Sb₂Te₃ with suitable composition is a promising novel phase‐change material used for PCM with high speed and good thermal stability performances. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)     

一种新颖的模糊形态联想记忆网络

模糊形态联想记忆网络FMAM具有较强的抗膨胀或腐蚀噪声能力，且可以模糊性解释。但抗混合噪声的能力很弱。而在实际中，随机噪声往往是混合型的，既有膨胀又有腐蚀噪声。为此提出了一种基于尺度空间的模糊形态联想记忆网络，并分析了其抗膨胀／腐蚀噪声和抗随机噪声的能力，它提高了自联想FMAM的抗随机噪声能力。通过仿真实验验证了该方法具有良好的性能。     

Ternary-Responsive Field-Effect Transistors and Multilevel Memories Based on Asymmetrically Functionalized Janus Few-Layer WSe2

Hybrids composed of 2D transition metal dichalcogenides with stimuli-responsive molecules are prototypical components for the development of multifunctional field-effect transistors (FETs), whose output currents can be remotely controlled by external inputs. Herein, ternary-responsive FETs based on a few-layer WSe₂ are realized by decorating the two opposite surfaces of the 2D semiconductor with different stimuli-responsive molecules in an asymmetric fashion: the bottom surface is interfaced with a photochromic diarylethene film and the top surface with a ferroelectric poly(vinylidene fluoride–trifluoroethylene) layer. This novel Janus ternary device architecture shows superior functional complexity compared with normal mono-stimuli-responsive FETs. The synergy between the two molecularly induced effects enables the devices to respond orthogonally to an electric field and light irradiation, with an enhanced output current modulation efficiency of 87%. The 9 ferroelectric and 84 photo-generated states ensure 756 current levels in a single device. The over 10 cycles of cyclic endurance and more than 1000 h of retention time confirm the reliability of each state, implementing the demand for high-density non-volatile memories, as well as enriching the diversification in “More than Moore” technologies.     

SONOS非易失性存储器件研究进展

随着半导体存储器件的小型化、微型化,传统多晶硅浮栅存储因为叠层厚度过大,对隧穿氧化层绝缘性要求过高而难以适应未来存储器的发展要求。最近,基于绝缘性能优异的氮化硅的SONOS非易失性存储器件,以其相对于传统多晶硅浮栅存储器更强的电荷存储能力、易于实现小型化和工艺简单等特性而重新受到重视。文章论述了SONOS非易失性存储器件的存储原理和存储性能的影响因素研究进展,并在材料、工艺与结构设计等方面对SONOS存储器件性能改进的研究进展情况进行了分析和讨论。     

Dynamical modeling of transport in MOS structures containing silicon nanocrystals for memory applications

A compact model that can be used to reproduce both quasi-static and dynamic characteristics of basic MOS cells with embedded Si-nc is presented. The structure is modeled through a device-like complex matrix of tunnel junctions, resulting in a time-dependent non-linear system of differential equations that is numerically solved, including calculation of the capacitance matrix, analytical tunneling expressions (direct and Fowler-Nordheim) for electrons/holes, and derivation of the effective tunneling area. The threshold evolution is calculated by monitoring the charge at each Si-nc as a function of time. The model is successfully validated against experimental data, showing its applicability to predict program/erase characteristics of nanocrystal memories as well as threshold voltage bit-to-bit dispersion as a consequence of geometrical non-uniformities in the nanocrystal layer position and/or gate areal coverage.     

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy

A two-port memory contains two duplicated sets of address decoders, which operate independently. Testing such memories requires the use of single-port tests as well as special two-port tests; the test strategy determines which tests have to be used. Many two-port memories have ports which are read-only or write-only; this impacts the possible tests for single-port and two-port memories, as well as the test strategy. In this paper the effects of interference and shorts between the address decoders of the two ports on the fault modeling are investigated. Fault models and their tests are introduced. In addition, the consequences of the port restrictions (read-only or write-only ports) on the fault models and tests are discussed, together with the test strategy.