“神龙一号”注入器研制

“神龙一号”注入器是直线感应加速器的束流源，它采用了感应叠加的高压加载方式，包括脉冲功率系统、感应腔、阴阳极杆、绝缘支撑、二极管和束流传输系统等子系统. 在研制中采用了径向绝缘支撑、对中支撑调节系统、类Pierce阴极等先进技术，以及二极管线圈内置和外径为800mm的铁氧体大环等创新. 参数测试显示，3.5MeV注入器达到了世界先进水平.     

基于单电子晶体管的数字滤波器硬件实现

基于互补型单电子晶体管（SET）逻辑门，提出了SET加法器、移位寄存器和ROM的单元电路。在讨论数字滤波器硬件实现原理基础上，由这三个单元电路实现了一个二阶IIR滤波器。SET的SPICE宏模型验证了设计的正确性。     

低功耗CMOS同或门的设计

讨论了现有异或门／同或（XOR／XNOR）门的设计,指出了基于不同逻辑类型设计的门电路的优缺点．考虑到基于CMOS设计的XNOR门相对于其他逻辑门在各方面的优点,重点分析了CMOSXNOR门结构对门电路性能的影响．提出了一个新颖的CMOS同或门电路．经PSPICE仿真模拟表明,新设计在没有增加管子数的前提下,改善了门电路的性能．将新设计应用到全加器的设计中,其功耗和功耗延迟积的改进分别达到了9．9％和11．6％．     

32位稀疏树加法器的设计改进与实现

提出了一种改进进位运算的32位稀疏树加法器。在对现有稀疏树加法器使用的进位运算算子"o"进行深入探讨的基础上,对该算子的表达式做出了适当改进,去除了原算子中进位输入须为0的前提条件,同时保留了原算子适用于稀疏树进位结构的运算特性。采用该改进算子的32位稀疏树加法器可以并行地产生进位输入分别为0和1时的一对"和"输出,并可根据需要选择输出相应的结果。在1.2V130nm典型CMOS工艺条件下,经由HSPICE仿真,改进的32位稀疏树加法器的关键路径延迟为10.8FO4。结果表明,该加法器在运算能力得到扩充的同时,在运算速度方面也具有一定优势。     

Enzyme-free and DNA-based universal platform for the construction of various logic devices based on graphene oxide and G-quadruplex

In the fields of biocomputing and biomolecular, DNA molecules are applicable to be regarded as data of logical computing platform that uses elaborate logic gates to perform a variety of tasks. Graphene oxide (GO) is a type of novel nanomaterial, which brings new research focus to materials science and biosensors due to its special selectivity and excellent quenching ability. G-quadruplex as a unique DNA structure stimulates the intelligent application of DNA assembly on the strength of its exceptional binding activity. In this paper, we report a universal logic device assisted with GO and G-quadruplex under an enzyme-free condition. Integrated with the quenching ability of GO to the TAMRA (fluorophore, Carboxytetramethylrhodamine) and the enhancement of fluorescence intensity produced by the peculiar binding of G-quadruplex to the NMM (N-methylmesoporphyrin IX), a series of basic binary logic gates (AND. OR. INHIBIT. XOR) have been designed and verified through biological experiments. Given the modularity and programmability of this strategy, two advanced logic gates (half adder and half subtractor) were realized on the basis of the same work platform. The fluorescence signals generated from different input combinations possessed satisfactory results, which provided proof of feasibility. We believe that the proposed universal logical platform that operates at the nanoscale is expected to be utilized for future applications in molecular computing as well as disease diagnosis.     

改进型booth华莱士树的低功耗、高速并行乘法器的设计

采用一种改进的基4 BOOTH编码和华莱士树的方案,设计了应用于数字音频广播(DAB)SOC中的FFT单元的24×24位符号定点并行乘法器.通过对部分积的符号扩展、(k:2)压缩器、连线方式和最终加法器分割算法的优化设计,可以在18.81 ns内完成一次乘法运算.使用FPGA进行验证,并采用chartered 0.35 μm COMS工艺进行标准单元实现,工作在50MHz,最大延时为18.81 ns,面积为14 329.74门,功耗为24.69 mW.在相同工艺条件下,将这种乘法器与其它方案进行比较,结果表明这种结构是有效的.     

High Performance CMOS Analog Arithmetic Circuits

Unique designs for CMOS analog arithmetic circuits are presented which perform addition (V₁ + V₂), subtraction (V₂ – V₁), add/invert –(V₁ + V₂), and multiply (V₁ × V₂). The circuit operation is based on the inherent square law of MOS transistor drain current when operating in the saturation region. Key features include: good linearity and accuracy, single ended voltage inputs and output, wide input and output range and no input bias voltages. The circuits can be directly coupled (no buffer) and serve as basic building blocks for analog signal processing implementations such as analog filters and adaptive equalizers. All circuits were implemented in 1.2 m CMOS technology.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

对称三进制光学加法器的进位直达通道设计

以对称三进制光学半加器为基础,提出了一个对称三进制光学全加器方案。主要介绍了进位直达并行通道在对称三进制光学全加器中的实现方案和工作原理,从而论证了实现对称三进制光学全加器的可行性。     

用于DDS系统相位累加器的加法器设计

直接数字频率合成器(DDS)具有频率转换时间短、分辨率高、输出相位连续等优点,是现代频率合成的重要技术之一。在分析了DDS基本原理的基础上,对DDS中的核心单元之一相位累加器进行了系统研究。分别利用镜像电路和超前进位全加器实现信号源累加器模块,进行模拟仿真并比较,结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。