排序方式: 共有40条查询结果,搜索用时 281 毫秒
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基带内插脉冲成形(BBIPS)滤波器是全数字调制器的核心模块之一.成形滤波运算是调制器中运算量最大的组成部分,因此它的高效实现对降低调制器的运算量有着积极的意义.标准的滤波运算需要大量的乘加操作,然而简单的查表操作就可以实现调制器的基带成形滤波功能.首先介绍BBIPS滤波的理论基础,然后给出用FPGA实现BBIPS滤波器的查找表方法,并详细介绍基于查找表的设计结构.采用该技术实现的全数字BBIPS滤波器不仅性能优越,而且具有很强的灵活性,可以针对不同码元速率、内插倍数、基带成形波形等参数在系统中方便地修改.符合数字通信软件化的趋势,在软件无线电中有广阔的应用前景. 相似文献
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一种新的图像实时放大技术 总被引:2,自引:0,他引:2
该文提出了一种视频图像整数倍放大的实时插值方案一改进的像素填充插值法,给出了其基本原理及软、硬件实现方法.与重复插值法、线性插值法、像素填充插值法和小波放大法等进行了比较,并给出了放大后图像的主观和客观评价。结果表明改进的像素填充插值法的效果明显优于其他实时放大方法,且其硬件实现并不复杂,可用于视频图像实时放大的软、硬件设计。 相似文献
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高速突发解调器的快速同步技术研究 总被引:1,自引:1,他引:0
突发通信中需重点考虑同步时间,提出了一种突发解调器方案,具有同步时间快、传输速率高的优点。重点介绍了符号定时和载波相位恢复,分析了定时估计算法和内插定时恢复中的关键点;分析了载波相位估计算法并结合工程实现提出了简化算法,分析了剩余载波频偏和相位估计时间的关系。Matlab定点仿真结果表明了该方案的可行性和有效性,最后根据提出的方案实现了90Mbps QPSK突发调制解调器。 相似文献
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针对传统的Mash结构由于各级失配导致信噪比低的问题,本文采用一阶相位累加器来实现传统的sigma-delta(Σ-Δ)架构,并将其采用硬件描述语言来实现,这样整个系统均在数字域实现,从根本上解决了各级间的失配问题.在插值滤波器的设计上,使用优化了的半带滤波器结构和级联积分梳状滤波器,节省了硬件资源.电路采用的是Magnachip 180nm 1P4M标准CMOS工艺,芯片面积只有0.2025mm2(0.45×0.45),实测芯片得到的信噪失真比(SNDR)达到90dB. 相似文献
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模拟下变频或基于多相滤波的数字正交变换都可能会在IQ路之间引入一个固定的分数倍采样点的延时,本文提出一种分数延时校正和符号定时同步相结合的方案,使两种误差在同一个环路中得到解决,符号定时同步环路采用Gardner时钟误差鉴相算法和拉格朗日内插算法,方案在1024QAM解调系统中验证成功。 相似文献
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Rajeev Ratan Sanjay Sharma Amit K. Kohli 《International Journal of Electronics》2013,100(12):1724-1734
In this article, the performance of quadrature amplitude modulation (QAM)-based single- and double-stage digital interpolators have been compared. The basic interpolator for up-sampling can be a combination of an expander unit with an interpolation lowpass filter in cascade. Complicated implementations can be done by connecting multiple expander and low-pass filter pairs in cascade. This article presents the efficient and effective implementation of digital interpolation systems for up-sampling of single- and double-stage digital interpolators. Comparison is done in terms of spectrum of generated signal, envelope power, modulated signal trajectory, input and output constellation and noise performance. In this article, the proposed interpolation filters have been simulated in Agilent's Advanced Design System (ADS). 相似文献
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Wei Qin 《International Journal of Electronics》2013,100(2):269-282
In this article, we propose a new frequency-domain weighted-least-squares method for designing high-accuracy interpolator (interpolation kernel) that reduces the number of the first-order derivative continuity constraints. By reducing the number of the first-order derivative constraints, we can increase the degree of freedom in the design, and thus have more flexibility to get more accurate design results. The interpolator consists of 6 piecewise polynomials of the third degree (cubic), and it is performed in the frequency-domain through minimising the weighted integrated-squared-error of the spectrum (frequency response). The weighting function is adjusted so as to ignore some insignificant frequency bands and put more emphasis on the important frequency bands. By imposing the continuity constraints on the interpolator itself as well as the reduced first-order derivative constraints at the contacting points, we get three free parameters of the interpolator. These three parameters are then optimised in such a way that the weighted integrated-squared-error of the frequency response is minimised. We will utilise a narrow-band example to demonstrate the performance improvement over other existing interpolators. 相似文献
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