一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

基于水印的图像认证和完整性保护技术

数字水印技术的发展为解决图像认证和完整性保护问题提供了新的思路。对用于篡改检测和图像认证的水印技术做了综述。数字水印技术根据其识别差错的能力分为四种类型:易损水印、半易损水印、混合水印和自嵌入水印。最后还对水印认证技术的安全性问题进行了讨论。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

网络信息安全技术综述

阐述了网络信息安全的三个组成方面,具体分析了在实际应用中的网络安全技术手段,探讨了国内外研究开发网络信息安全技术的现状、发展趋势及我们所应着重采取的策略.     

一种异地库房管理中远程数据维护方法的研究与应用

介绍了在异地库房管理中，采用C／S结构和远程数据库访问技术等实现的对远程数据维护的一种方法。通过该方法开发的远程数据传输系统，实现了远程客户端对服务器的通信，完成了远程数据在后台服务器的集中管理和服务器对远程数据的格式、类型等的控制，同时保证了远程客户端对服务器操作的并发性，客户端数据和服务器数据的完整性、安全性以及远程客户端数据与后台服务器数据的一致性，有效地维护了远程数据。该系统已成功运用于库房管理之中。     

Pinhole density measurements of barriers deposited on low-k films

Evaluation of diffusion barrier integrity is an important issue in advanced interconnects. A diffusion barrier separating Cu from low-k must be as thin as possible and must not contain pinholes. We have developed a method for measuring pinhole density in diffusion barriers deposited on low-k materials. The method employs ellipsometric porosimetry for measuring diffusion of toluene in a porous low-k film beneath the barrier in question.     

Macromodeling of high-speed interconnects by positive interpolation of vertical segments

In this paper a novel macromodeling scheme is presented to model the per unit of length (p.u.l.) parameters of uniform transmission lines. In particular, it is focused on single on-chip interconnects, because their p.u.l. parameters are influenced by the presence of semiconductor (s) and as such exhibit a strong frequency-dependency, making the modeling process harder. Starting from a set of very accurate tabulated data samples, obtained by two-dimensional electromagnetic modeling, rational models for the four p.u.l. parameters are constructed. The novelty of the approach lies in the fact that the rational models are positive by construction and that a controllable accuracy is obtained. These models can then further be used to construct multivariate models, e.g., for variability analysis. Here, the novel scheme is applied to an on-chip inverted embedded microstrip line, of which the signal integrity behavior is assessed in both the frequency and the time domain, demonstrating the applicability of the macromodels.     

基于TCM的安全Windows平台设计与实现

为了解决Windows系统的完整性度量与证明问题,提出了一种基于可信密码模块TCM (trusted cryptography module)的安全Windows平台方案。通过扩展Windows内核实现了2种安全模式：在度量模式下,所有加载的可执行程序都会被度量,度量值由TCM提供保护和对外认证;在管控模式下,度量值会进一步与管理员定制的白名单进行匹配,禁止所有不在白名单中的程序执行。实验分析表明,该方案可以增强Windows系统的安全性,抵抗一些软件攻击行为;同时,系统平均性能消耗在20~30 ms之间,不会影响Windows的正常运行。     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.