COPART:一种面向约束条件的自适应软硬件划分算法

本文介绍一种将自适应算法、遗传算法和列表调度算法结合起来应用于软硬件划分问题的算法COPARTART，并提出了一种基于约束条件的开销系数自适应调整方法，该方法所获得的划分结果能够良好体现设计目标。     

一种基于Zynq-7000+AD9361的通用调制平台设计

针对一般调制平台互联性差、灵活性差、复用性差等问题,采用软硬件协同设计和部分动态可重配置等技术,设计了一种基于Zynq-7000和AD9361的通用调制平台。采用16APSK和QPSK的调制方式对通用调制平台的设计进行验证,其中平方根升余弦成形滤波器采用查找表形式的多相滤波器结构实现,该实现方法只用到加法运算。测试结果表明,在不同Zynq-7000开发板和不同调制方式下,替换部分硬件功能模块和修改软件配置,平台均能正常工作。与传统调制平台相比,本平台的设计以及功能实现具有灵活性强、复用性高等特点,具有广阔应用前景。     

基于资源受限的软硬件划分方法

本文提出了一种在硬件资源受限的情况下进行软硬件划分的一种方法。以贪婪算法(greedy)作为划分的核心，并对所抽取的划分图进行结点的预先分类，减小贪婪算法探索的设计空间，加速算法的执行。通过反复地迭代，获得了最终的软硬件划分选择。实验证明，这种软硬件划分的方法具有高效率及高面积利用率的特点。     

LYCOS: the Lyngby Co-Synthesis System

This paper describes the LYCOS system, an experimental co-synthesis environment. We present the motivation and philosophy of LYCOS and after an overview of the entire system, the individual parts are described. We use a single CPU, single ASIC target architecture and we describe the techniques we use to estimate metrics concerning hardware, software and communication in this architecture. Finally we present a novel partitioning technique called PACE, which has shown to produce excellent results, and we demonstrate how partitioning is used to do design space exploration.     

A New Real Time Object Segmentation and Tracking Algorithm and its Parallel Hardware Architecture

Most of the emerging content-based multimedia technologies are based on efficient methods to solve machine early vision tasks. Among other tasks, object segmentation is perhaps the most important problem in single image processing. The solution of this problem is the key technology of the development of the majority of leading-edge interactive video communication technology and telepresence systems. The aim of this paper is to present a robust framework for real-time object segmentation and tracking in video sequences taken simultaneously from different perspectives. The other contribution of the paper is to present a new dedicated parallel hardware architecture. Its composed of a mixture of Digital Signal Processing (DSP) and Field Programmable Gate Array (FPGA) technologies and uses the Content Addressable Memory (CAM) as a main processing unit. Experimental results indicate that small amount of hardware can deliver real-time performance and high accuracy. This is an improvement over previous systems, where execution time of the second-order using a greater amount of hardware has been proposed.Mahmoud Meribout (BS85, M91). Received the PhD degree in Electronic Engineering from the University of Technology of Compiegne (France), in January 3rd 1995. He worked one year as an Associate Researcher, where he has been involved in some industrial projects related to hardware board design and video processing. FromNovember 1995 to October 2000, he has beenworking in Japan, with NTT and NEC corporations respectively, where he has been involved in several projects related to hardware & software design of next generation multimedia and networking equipments. He is holding several Japanese and American patents related to this particular topic. In 1998, he has received the NTT best award for his research and development records.Maamouru Nakanishi received the B.S. and M.S. in Electronics in 1985 and 1987 respectively, all from Kyoto University. Since 1987, he has been engaged in R&D of parallel processing architectures, memory-processor integration technology at NTT Corporation (Tokyo, Japan), when he has been involved in research on Advanced Content Addressable Memory applied to video processing. In 1998, he has received the NTT best award for his research and development records.     

Optimized RTL Code Generation from Coarse-Grain Dataflow Specification for Fast HW/SW Cosynthesis

This paper presents a new methodology of automatic RTL code generation from coarse-grain dataflow specification for fast HW/SW cosynthesis. A node in a coarse-grain dataflow specification represents a functional block such as FIR and DCT and an arc may deliver multiple data samples per block invocation, which complicates the problem and distinguishes it from behavioral synthesis problem. Given optimized HW library blocks for dataflow nodes, we aim to generate the RTL codes for the entire hardware system including glue logics such as buffer and MUX, and the central controller. In the proposed design methodology, a dataflow graph can be mapped to various hardware structures by changing the resource allocation and schedule information. It simplifies the management of the area/performance tradeoff in hardware design and widens the design space of hardware implementation of a dataflow graph. We also support Fractional Rate Dataflow (FRDF) specification for more efficient hardware implementation. To overcome the additional hardware area overhead in the synthesized architecture, we propose two techniques reducing buffer overhead. Through experiments with some real examples, the usefulness of the proposed technique is demonstrated.

基于FPGA的USB圭控芯片软硬件协同设计与验证

设计了一款采用PowerPC架构的USB1．1主机控制器芯片,并对该芯片进行软硬件协同验证。通过内嵌PowerPC和USB主机IP核的FPGA系统,辅以外部收发器电路、驱动、应用程序和文件系统,完成了对U-Disk和HID两类典型USB应用的测试,验证结果表明该USB主机芯片设计可以符合USB技术规范,并能和其他厂家的设备兼容。     

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.Sebastien Bilavarn received the M.S. degree from Rennes University (France) in 1998 and the PhD degree in Electrical Engineering from South Brittany University in 2002. Since June 2002, he works as a post-doc fellow at Signal Processing Institute, Swiss Federal Institute of Technology (EPFL). Sebastiens research interests include design methodologies for embedded systems, reconfigurable computing and Digital Signal Processing. Currently, his work focuses on using Adaptive Computing Systems to optimise computer architectures, which is a collaboration with the Architecture Research Lab of the System Technology Labs, Intel Corporation.Eric Debes received a M.S. in Electrical and Computer Engineering from Supélec, France in 1996, a M.S. in Electrical Engineering from the Technical University Darmstadt, Germany in 1997 and a PhD in Signal Processing from the Swiss Federal Institute of Technology. Since 2001 he has been a Researcher in the Architecture Research Lab of the System Technology Labs, Intel Corporation, Santa Clara, California. Erics research interests include image and video coding and processing algorithms as well as computer architecture and parallelism. At Intel he has been working together with different processor teams and microarchitecture research groups on the definition of new media and communication features (including new SIMD and streaming instructions, multicore processors and low-power architectures) in the CPU and the chipset to provide better media application performance and end user quality of service with a given system and processor power envelope and/or energy budget. More recently Eric has been working on system-on-chip modelling, processor and system power estimation and architecture design space exploration for consumer electronics applications. He is a member of the IEEE, of the ACM and of the SPIE.Pierre Vandergheynst received the M.S. degree in physics and the Ph.D. degree in mathematical physics from the Université catholique de Louvain, Belgium, in 1995 and 1998 respectively. From 1998 to 2001, he was a Postdoctoral Researcher with the Signal Processing Laboratory, Swiss Federal Institute of Technology (EPFL), in Lausanne, Switzerland. He is now an Assistant Professor of Visual Information Processing at EPFL, where is research focuses on computer vision, data processing and mathematical tools for visual information processing. Prof. Vandergheynst is Co-Editor-in-Chief of Signal Processing and member of the IEEE.Jean-Philippe Diguet received the M.S degree and the PhD degree from Rennes University (France) in 1993 and 1996 respectively. His thesis focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. From 1997 to 2002, he has been an associated professor at the South Brittany University and member of the LESTER laboratory. In 2003/04, he has initiated and created an innovating company in the domain of short range wireless communications. In 2004, he obtains a CNRS researcher position. His current work focuses on design space exploration of embedded systems, real-time scheduling in the context of hardware/software architecture configurations. Within the LESTER laboratory, he heads the “Design Trotter” team focusing on EDA methods and tools.     

嵌入式系统技术研究及其开发实例

简述了嵌入式系统的定义及其应用现状、发展趋势 ,并详细分析了嵌入式系统的特点、结构和嵌入式系统设计的一些重要技术。最后给出了一个应用实例 ,介绍了该实例的总体功能描述 ,硬件平台总体结构 ,Win dowsCE .net的软件开发概述及嵌入式软件的开发流程。     

Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases

Tecs is a test case development methodology for the functional validation of large electronic systems, typically consisting of several custom hardware and software components. The methodology determines a hierarchical top-down test case development process including test case specification, validation, partitioning and implementation. The test case development process addresses the functional validation of the system and its components such as ASICs, boards, HW and software modules; it does not facilitate timing or performance verification. The system functions are used to define test cases at the system level and to derive sub-functions for the system components. Test cases are specified, using a special purpose formalism, and validated before they are applied to the system under test. Furthermore, we propose a technique to partition test cases corresponding to the partitioning of the system into sub-systems and components. This technique can significantly reduce system simulation time because it allows the full validation of system functions by simulation at the sub-system and component level. The system model need only be simulated with a reduced set of stimuli to validate the interfaces between sub-systems. We present a test case specification language and tools that support the proposed methodology. The validation of a switching function illustrates methodology, language, and tools.