LDD方法在提高电路工作电压中的应用研究

研究了利用轻掺杂漏结构来制作高电源电压器件的工艺方法。分析了ＬＤＤ结构参数对器件击穿特性的影响，并结合实验结果对Ｎ＾－区的注入剂量，长度及引入的串联电阻进行了优化设计。     

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

碳纳米管场效应晶体管紧凑模型研究进展

随着摩尔定律逼近极限,碳纳米管场效应晶体管(CNTFET)被认为是5 nm以下CMOS晶体管的有力替代者。CNTFET具有准一维结构,栅极可有效控制导电沟道的导通/关断;同时,载流子在沟道内可实现近弹道输运,具有极高的迁移率。因此,CNTFET在低电压环境下,可提供较大的电流传输能力,为实现纳米级超大规模模拟/逻辑电路提供了解决方案。文章综述了CNTFET紧凑模型的发展现状,分析了现阶段面临的漏极电流精确模型、隧穿效应、寄生效应、多纳米管模型等存在的问题,重点探讨了针对这些问题的解决方案。最后对该紧凑模型未来的应用前景进行了讨论。     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

宽带单片低噪声放大器的增益温度补偿

分析了PHEMT的增益-温度特性和漏电流-温度特性,发现PHEMT增益和漏电流都是随温度的升高而降低,并发现了一定栅宽的PHEMT在大于某一频率时,其增益受温度变化较小的原因.提出了两种自动温度补偿的方法,并分析了每种方法的温度补偿原理.串联源电阻的温度补偿可使PHEMT的漏电流基本保持不变,在一定程度上能降低温度对增益的影响.而自动栅压温度补偿则是强温度补偿,它可随温度的升高,自动提高栅极电压,提高PHEMT的跨导,从而大大减少温度对增益的影响,达到温度补偿的目的.把这两种自动温度补偿的方法结合应用到宽带低噪声放大器中,发现补偿效果良好.试验发现温度补偿后,温度从-55℃~+85℃时和-55℃~+125℃时,放大器的增益在6GHz时的降差分别减小了60%和51%,较大地改善了放大器的温度-增益性能.     

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET. Specifically, metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS) NC FinFETs are compared, in order to figure out the effect of the internal metal layer on the GIDL effect. To analyze the impact of the polarization gradient on the GIDL effect in NC FinFET, a polarization gradient coefficient is varied. For MFMIS, the polarization gradient doesn't significantly affect the device performance. The subthreshold swing improves but the GIDL effect deteriorates because of the “uniform” NC effect in channel region. For MFIS, the device performance is explicitly affected by the polarization gradient. Smaller polarization gradients result in non-uniform NC effect in channel region, resulting in severe GIDL effects. On the other hand, higher polarization gradients alleviate GIDL effects.     

A Low On-Resistance SOI LDMOS using a Trench Gate and a Recessed Drain Ge Rui(葛锐), Luo Xiaorong(罗小蓉)?, Jiang Yongheng(蒋永恒), Zhou Kun(周坤),

本文提出了一种超低比导通电阻(R_on,sp) SOI槽栅凹漏MOSFET(TGRD MOSFET)。正向导通时,槽栅和凹漏的结构增加了导电区域,缩短了电流流经的路径,从而降低了比导通电阻。并且此结构中采用了RESURF结构提高了漂移区浓度,进一步降低了比导通电阻。当TGRD MOSFET的半个元胞尺寸为6.5μm时,它的击穿电压为97V,R_on,sp为0.985mΩ.cm₂。与SOI槽栅MOSFET(TG MOSFET)和常规MOSFET(Conventional MOSFET)相比,在相同的BV下,TGRD MOSFET的R_on,sp分别地降低了46%和83%。或者在相同的R_on,sp下,与SOI槽栅槽漏MOSFET(TGTD MOSFET)相比, BV提高了37%。     

SOI CMOS器件研究

利用0.35μm工艺条件实现了性能优良的小尺寸全耗尽的器件硅绝缘体技术(SOI)互补金属氧化物半导体(FD SOI CMOS)器件,器件制作采用双多晶硅栅工艺、低掺杂浓度源/漏(LDD)结构以及突起的源漏区。这种结构的器件防止漏的击穿,减小短沟道效应(SCE)和漏感应势垒降低效应(DIBL);突起的源漏区增加了源漏区的厚度并减小源漏区的串联电阻,增强了器件的电流驱动能力。设计了101级环形振荡器电路,并对该电路进行测试与分析。根据在3V工作电压下环形振荡器电路的振荡波形图,计算出其单级门延迟时间为45ps,远小于体硅CMOS的单级门延迟时间。     

高漏偏压下AlGaN/GaN HEMT噪声性能的研究

The advent of fully integrated GaN PA-LNA circuits makes it meaningful to investigate the noise performance under high drain bias. However, noise performance of AlGaN/GaN HEMTs under high bias has not received worldwide attention in theoretical studies due to its complicated mechanisms. The noise value is moderately higher and its rate of increase is fast with increasing high voltage. In this paper, several possible mechanisms are proposed to be responsible for it. Impact ionization under high electric field incurs great fluctuation of carrier density, which increases the drain diffusion noise. Besides, higher gate leakage current related shot noise and a more severe self-heating effect are also contributors to the noise increase at high bias. Analysis from macroscopic and microscopic perspectives can help us to design new device structures to improve noise performance of AlGaN/GaN HEMTs under high bias.     

PCB行业实施清洁生产取得的成效（2）——以汕头超声印制板（二厂）有限公司为例

汕头超声印制板（二厂）公司藉“节能减排”的契机，打破经验思维的束缚，把汕头超声印制板公司的成果和理念成功运用到本公司的清洁生产工作中，创造了良好的经济效益和环境效益。