一种具有O信息复杂度的高速crossbar调度算法

本文提出一种可扩展性强的高速crossbar调度算法——iRGRR(iterative request-grant-based round-robin),它通过简化处理流程和减小调度开销,克服了传统算法(例如iSLIP^[1]、PIM^[2])可扩展性差的缺陷.iRGRR将控制信息复杂度从O(N)级大大减小到O(logN)级,具有良好的可扩展性,可应用于太比特交换机/路由器中.仿真结果表明,在各种不同的均匀和非均匀业务流下,iRGRR能够获得与iSLIP几乎相同的性能.另外,iRGRR比iSLIP具有更好的公平性以及更加易于用硬件实现.     

一种可提供QoS保障的新型交换结构

本文采用带缓存交叉开关作为核心交换单元,构建了一种空分复用扩展的联合输入/交叉节点/输出排队(SDM-CICOQ)交换结构,从理论上证明了当扩展因子为2时,SDM-CICOQ交换结构可以获得100%的吞吐量,并且能够完全模拟输出排队(OQ)交换结构,从而能够提供服务质量(QoS)保障.本文还给出了一种层次化优先级调度(HPS)方案作为SDM-CICOQ交换结构调度机制的工程设计参考,仿真结果表明采用HPS调度方案SDM-CICOQ交换结构可获得良好的性能.     

Electrical properties of Pt interconnects for passive crossbar memory arrays

We report on the fabrication and the electrical characterization of platinum interconnects for novel non-volatile memory technologies. These nanowires present an important and essential contribution to the deep nanometer scaling of alternative architectures beyond CMOS, e.g. nanocrossbar arrays with resistance switching junctions. The nanowires, which have a thickness of 25 nm and a width ranging from 200 nm down to 40 nm, were patterned using electron beam direct writing. They were deposited by UHV electron beam evaporation in combination with a lift-off process.The electrical characteristic is increasingly affected by the contribution of surface effects like scattering at grain boundaries and scattering at the surfaces as the wire dimensions become smaller. With decreasing width of the platinum wire an increasing resistivity was observed, which is consistent with the theories of Fuchs-Sondheimer and Mayadas-Shatzkes. Our studies have shown that the investigated structures possess a high stability concerning the operational current densities up to 4 × 10⁷ A/cm², and an additional annealing step results in an improvement of the electrical wire properties, which is explained by a higher quality of the grain boundaries and side walls.     

Exhaustive Output Arbitration of Input Buffered Switch with Buffered Crossbar

We propose a new arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, an exhaustive polling method is used to decrease the synchronization. Using an approximate analysis, we explain how the proposed method improves the switch performance. Also, using computer simulations, we show the proposed method outperforms the previous methods under burst traffic.     

A Review of Three‐Dimensional Resistive Switching Cross‐Bar Array Memories from the Integration and Materials Property Points of View

Issues in the circuitry, integration, and material properties of the two‐dimensional (2D) and three‐dimensional (3D) crossbar array (CBA)‐type resistance switching memories are described. Two important quantitative guidelines for the memory integration are provided with respect to the required numbers of signal wires and sneak current paths. The advantage of 3D CBAs over 2D CBAs (i.e., the decrease in effect memory cell size) can be exploited only under certain limited conditions due to the increased area and layout complexity of the periphery circuits. The sneak current problem can be mitigated by the adoption of different voltage application schemes and various selection devices. These have critical correlations, however, and depend on the involved types of resistance switching memory. The problem is quantitatively dealt with using the generalized equation for the overall resistance of the parasitic current paths. Atomic layer deposition is discussed in detail as the most feasible fabrication process of 3D CBAs because it can provide the device with the necessary conformality and atomic‐level accuracy in thickness control. Other subsidiary issues related to the line resistance, maximum available current, and fabrication technologies are also reviewed. Finally, a summary and outlook on various other applications of 3D CBAs are provided.     

一种新型可扩展的多级多平面分组交换结构的图论模型与性能分析

该文提出了一种新型可扩展的多级多平面(MPMS)分组交换结构。首先建立了MPMS的图论模型,定量地描述了MPMS中相邻连通性和端口可达性,定义了MPMS的均衡顶点和竞争顶点,并证明了MPMS决定交换性能的输入端口与输出端口间的无阻塞条件。从性能参数和结构复杂度等方面与单级交叉开关做了对比分析,结果表明MPMS可以获得P倍的最大端口速率,平方倍的最大端口数,线性比例增长的结构复杂度,具有良好的可扩展性。     

单块晶体集成的N×N纵横开关网络及其控制算法

设计了一种单块晶体集成的n×n纵横开关(Crossbar)网络。通过综合考虑晶体的双折射和全内双反射现象,以及晶体的电光效应,将构成n×n纵横开关网络的所有单元器件都集成到一块具有电光效应的双折射晶体上。同时,给出了该网络的控制算法,通过对开关工作状态的控制,可以实现任意输入输出通道之间的无阻塞连接。这种单块晶体集成的纵横开关网络具有能量损耗低、无阻塞、易安装、抗干扰等优点,适合于全光网络发展的需要。     

多片FPGA系统互连结构研究

本文在分析现有多FPGA系统互连拓朴结构的基础上，指出其最佳形式，即硬布线和可编程布线相结合，优势互补，并提出了一种新的拓朴结构——最大权生成树与交叉开关相结合，详述了其设计流程和算法。     

并行处理阵列中光电混合光纤Crossbar互连网络的研制

本文综述了用于三维光电混合并行处理器阵列系统中的双向可编程多样重构光纤Crossbar互连网络。重点介绍了基于光纤通信的Crossbar互连网络中光纤互连器的设计原理与制作方法,并给出一种具体的电路图,用自制的伪随机码发生器测试了器件的整体性能,而后进行了应用性联机测试。结果表明,该光纤互连器能很好地满足系统中处理器20Mbps传输速率的要求,电路简单,具有通用性和较高的性能价格比。     

LHFS-支持公平服务的CICQ混合调度策略

 针对现有联合输入交叉点排队交换结构(CICQ,Combined Input and Cross-point Queuing)调度策略无法提供基于"流"的服务质量保障,探讨了在CICQ交换结构实施基于流调度的可能性,提出一种能够为到达流提供公平服务的分层混合公平服务调度策略—LHFS(Layered and Hybrid Fair Scheduling).LHFS对每个输入、输出端口可独立地进行变长分组交换,其算法复杂度为O(1),具有良好可扩展特性.理论分析结果表明,LHFS能够为业务流提供时延上限和公平性保障.最后,基于SPES(Switching Performance Evaluation System)仿真系统对LHFS的性能进行了评估.