一种模拟协处理器的实现架构

提出了一种模拟协处理器的设计思想,介绍了一种利用成熟模拟电路的运算特性进行波形变换,并实现高速复杂波形的方法。即先利用DSP的灵活性产生一种低阶的简单波形,再利用成熟模拟电路的运算特性(如对数运算、乘方运算、微/积分运算等)将前级电路产生的简单波形变换为所需的高阶复杂波形。由于模拟协处理器的应用,DSP的计算任务由计算超越函数简化为计算非超越函数,计算量和采样点数都大幅减少,使得常规的DSP芯片就能够完成必要的波形计算和其它任务(如编码运算)。该方法结合了数字电路和模拟电路各自的优势,能够消除数字电路(如DSP、DDS等)实现一些高速复杂调制时常见的几种数字波纹。工程实践和MATLAB仿真证明,此设计思想具有良好的推广和应用价值。     

Processor Enhancements for Media Streaming Applications

The development of more processing demanding applications on the Internet (video broadcasting) on one hand and the popularity of recent devices at the user level (digital cameras, wireless videophones, ...) on the other hand introduce challenges at several levels. Today, such devices present processing capabilities and bandwidth settings that are inefficient to manage scalable QoS requirements in a typical media delivery framework. In this paper, we present an impact study of such a scalable data representation optimized for QoS (Matching Pursuit 3D algorithms) on processor architectures to achieve the best performance and power efficiency. A review of state of the art techniques for processor architecture enhancement let us expect promising opportunities from the latest developments in the reconfigurable computing research field. We present here the first design steps of an efficient reconfigurable coprocessor especially designed to cope with future video delivery and multimedia processing requirements. Architecture perspectives are proposed with respect to low development cost constraints, backward compatibilty and easy coprocessor usage using an original strategy based on a hardware/software codesign methodology.Sebastien Bilavarn received the M.S. degree from Rennes University (France) in 1998 and the PhD degree in Electrical Engineering from South Brittany University in 2002. Since June 2002, he works as a post-doc fellow at Signal Processing Institute, Swiss Federal Institute of Technology (EPFL). Sebastiens research interests include design methodologies for embedded systems, reconfigurable computing and Digital Signal Processing. Currently, his work focuses on using Adaptive Computing Systems to optimise computer architectures, which is a collaboration with the Architecture Research Lab of the System Technology Labs, Intel Corporation.Eric Debes received a M.S. in Electrical and Computer Engineering from Supélec, France in 1996, a M.S. in Electrical Engineering from the Technical University Darmstadt, Germany in 1997 and a PhD in Signal Processing from the Swiss Federal Institute of Technology. Since 2001 he has been a Researcher in the Architecture Research Lab of the System Technology Labs, Intel Corporation, Santa Clara, California. Erics research interests include image and video coding and processing algorithms as well as computer architecture and parallelism. At Intel he has been working together with different processor teams and microarchitecture research groups on the definition of new media and communication features (including new SIMD and streaming instructions, multicore processors and low-power architectures) in the CPU and the chipset to provide better media application performance and end user quality of service with a given system and processor power envelope and/or energy budget. More recently Eric has been working on system-on-chip modelling, processor and system power estimation and architecture design space exploration for consumer electronics applications. He is a member of the IEEE, of the ACM and of the SPIE.Pierre Vandergheynst received the M.S. degree in physics and the Ph.D. degree in mathematical physics from the Université catholique de Louvain, Belgium, in 1995 and 1998 respectively. From 1998 to 2001, he was a Postdoctoral Researcher with the Signal Processing Laboratory, Swiss Federal Institute of Technology (EPFL), in Lausanne, Switzerland. He is now an Assistant Professor of Visual Information Processing at EPFL, where is research focuses on computer vision, data processing and mathematical tools for visual information processing. Prof. Vandergheynst is Co-Editor-in-Chief of Signal Processing and member of the IEEE.Jean-Philippe Diguet received the M.S degree and the PhD degree from Rennes University (France) in 1993 and 1996 respectively. His thesis focused on the estimation of hardware complexity and algorithmic transforms for architectural synthesis. Then he joined the IMEC in Leuven (Belgium) where he worked as a post-doc fellow on the minimization of the power consumption of memories at the system-level. From 1997 to 2002, he has been an associated professor at the South Brittany University and member of the LESTER laboratory. In 2003/04, he has initiated and created an innovating company in the domain of short range wireless communications. In 2004, he obtains a CNRS researcher position. His current work focuses on design space exploration of embedded systems, real-time scheduling in the context of hardware/software architecture configurations. Within the LESTER laboratory, he heads the “Design Trotter” team focusing on EDA methods and tools.     

一种嵌入式SIMD协处理器地址产生器的设计

文章介绍了一种新的嵌入式SIMD协处理器地址产生器.该地址产生器主要完成地址计算和协处理器指令的场抽取功能.为了提高协处理器的性能,地址产生器中设计了新的传送路径.该传送路径能够不通过地址产生器中的ALU而把数据送入寄存器中,这个传送路径能够减少ldN指令的一个延迟周期.在SMIC0.18微米标准库单元下,该地址产生器的延迟能够满足周期为10ns的协处理器.     

AES协处理器IP核的设计与实现

用Verilog语言设计了一种AES加密解密协处理器,并利用Xilinx公司的ISE8．2i软件和Spartan-3系列的FPGA对其进行验证和优化。本设计使用了少量的资源达到了比较高的数据吞吐量,形成可重用的AES加密解密协处理器的IP核。     

Reconfigurable Filter Coprocessor Architecture for DSP Applications

Digital Signal Processing (DSP) is widely used in high-performance media processing and communication systems. In majority of these applications, critical DSP functions are realized as embedded cores to meet the low-power budget and high computational complexity. Usually these cores are ASICs that cannot be easily retargeted for other similar applications that share certain commonalities. This stretches the design cycle that affects time-to-market constraints. In this paper, we present a reconfigurable high-performance low-power filter coprocessor architecture for DSP applications. The coprocessor architecture, apart from having the performance and power advantage of its ASIC counterpart, can be reconfigured to support a wide variety of filtering computations. Since filtering computations abound in DSP applications, the implementation of this coprocessor architecture can serve as an important embedded hardware IP.     

运动估计协处理器的设计

设计了一个运动估计协处理器,用来从硬件的角度解决图像匹配的实时性问题.首先介绍图像处理中的运动估计技术,然后介绍运动估计技术中常用的块匹配算法及判据的选择,最后详细介绍了运动估计协处理器的设计及其实现.     

Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality

The computational power required in many multimedia applications is well beyond the capabilities of today's multimedia systems. Therefore, the embedding of additional high-performance accelerator multimedia components into these systems is most decisive. This paper presents the embedding of multimedia components into computer systems using reconfigurable coprocessor boards. The goal of those reconfigurable platforms which can be adapted to several applications and which include programmable digital signal processors, control and memory devices as well as dedicated multimedia ASICs is worked out. On the way to such a platform four ASICs for image and text processing are presented. The embedding of these components into a computing system using a CardBus-based coprocessor board is shown. Such a reconfigurable coprocessor board is an important intermediate stage on the way to future hybrid reconfigurable systems on chip.     

AVS熵解码与DSP实现

阐述了AVS标准的进展情况及AVS标准的特点,重点介绍了AVS熵解码的原理和采用Equator公司MAP-CABSP-15处理器中的协处理器(Vlx)实现AVS熵解码的方法.     

基于高性能浮点乘累加器的浮点协处理器设计

复杂运算中经常需要处理取值范围大、精度高的浮点型数据,一般的低端嵌入式内核中没有浮点硬件单元,采用软件模拟浮点运算往往不能满足实时性要求。现研究基于高性能浮点乘累加的通用浮点协处理器设计与实现,重点研究提升浮点运算能力、减少硬件开销等关键技术。实验结果显示向量浮点协处理器运算周期减少40％以上。     

H.264硬件编码器设计

介绍了H．264硬件编码器的发展状况及设计要点,分析比较了两种不同设计思路的实现架构特点,引入了多核编码器设计的概念,提出了两级指令发射概念,实现了模块多模式可配置操作。