零维到三维结构中三核铜自旋阻挫簇单元的磁构关系和反对称交换

量子自旋液体是最近几年刚被人们证实除铁磁体、反铁磁体之外的第三种磁性类型,因其有望解释高温超导的运行机制、改变计算机硬盘信息存储方式而在物理、材料等领域备受关注。自旋阻挫作为量子自旋液体的最小单元可能是解开量子自旋液体诸多问题的钥匙,所以在磁学、电学研究领域再一次成为人们研究的热点。基于文献报道的三核铜配合物[Cu3(μ3-OH)(μ-OPz)3(NO3)2(H2O)2]·CH3OH(1),我们合成了三维金属有机框架配合物{[Ag(HOPz)Cu3(μ3-OH)(NO3)3(OPz)2Ag(NO3)]·6H2O}n(2)(HOPz=甲基(2-吡嗪基)酮肟),并从自旋阻挫的角度对二者磁性质进行对比和详细分析。磁化率数据表明自旋间有很强的反铁磁相互作用和反对称交换。通过包含各向同性和反对称交换的哈密顿算符对两者磁学数据进行拟合并研究其磁构关系,所获最佳拟合参数为:配合物1:Jav=-426 cm^-1,g⊥=1.83,g∥=2.00;配合物2:Jav=-401 cm^-1,g⊥=1.85,g∥=2.00。     

Mononuclear and Dinuclear Copper Complexes of Tridentate Redox-active Ligands with Tunable H-bonding Donors: Structure,Spectroscopy and H+/e− Reactivity

In this research article, we describe the synthesis and characterization of mononuclear and dinuclear Cu complexes bound by a family of tridentate redox-active ligands with tunable H-bonding donors. The mononuclear Cu-anion complexes were oxidized to the corresponding “high-valent” intermediates by oxidation of the redox-active ligand. These species were capable of oxidizing phenols with weak O−H bonds via H-atom abstraction. Thermodynamic analysis of the H-atom abstractions, which included reduction potential measurements, pK_a determination and kinetic studies, revealed that modification of the anion coordinated to the Cu and changes in the H-bonding donor did not lead to major differences in the reactivity of the “high-valent” CuY complexes (Y: hydroxide, phenolate and acetate), which indicated that the tridentate ligand scaffold acts as the H⁺ and e⁻ acceptor.     

Can a Procedure for the Growth of Single-layer Graphene on Copper be used in Different Chemical Vapor Deposition Reactors?

In the last decade, catalytic chemical vapor deposition (CVD) has been intensively explored for the growth of single-layer graphene (SLG). Despite the scattering of guidelines and procedures, variables such as the surface texture/chemistry of catalyst metal foils, carbon feedstock, and growth process parameters have been well-scrutinized. Still, questions remain on how best to standardize the growth procedure. The possible correlation of procedures between different CVD setups is an example. Here, two thermal CVD reactors were explored to grow graphene on Cu foil. The design of these setups was entirely distinct, one being a “showerhead” cold-wall type, whereas the other represented the popular “tubular” hot-wall type. Upon standardizing the Cu foil surface, it was possible to develop a procedure for cm²-scale SLG growth that differed only by the carrier gas flow rate used in the two reactors.     

Highly Selective Copper‐Catalyzed Asymmetric [3+2] Cycloaddition of Azomethine Ylides with Acyclic 1,3‐Dienes

The first examples of the catalytic asymmetric 1,3‐dipolar cycloaddition of azomethine ylides with acyclic activated 1,3‐dienes (and 1,3‐enynes) are described. Under copper catalysis, a selective cycloaddition at the terminal γ,δ‐C?C bond is observed. In addition, depending on the ligand used, either the exo or the endo adduct can be obtained with high selectivity. Under appropriate reaction conditions, the acyclic 1,6‐addition product is detected, suggesting a stepwise mechanism. The resulting C4‐alkenyl‐substituted pyrrolidines are suitable substrates for further access to polycyclic systems, as highlighted by the preparation of hexahydrochromeno[4,3‐b]pyrrole and the tetracyclic core of the alkaloid gracilamine.     

流变仪在覆铜板工序中的应用

本文简要叙述利用流变仪对覆铜箔层压板生产工序中的胶液和半固化片参数进行控制,从而更好地保证胶液和 半固化片性状的一致性,以有利于控制板材流胶和品质。     

新型的芯片间互连用CMOS/BiCMOS驱动器

从改善不同类型 IC芯片之间的电平匹配和驱动能力出发 ,设计了几例芯片间接口 (互连 )用 CMOS/Bi CMOS驱动电路 ,并提出了采用 0 .5 μm Bi CMOS工艺 ,制备所设计驱动器的技术要点和元器件参数。实验结果表明所设计驱动器既具有双极型电路快速、大电流驱动能力的特点 ,又具备 CMOS电路低压、低功耗的长处 ,因而它们特别适用于低电源电压、低功耗高速数字通信电路和信息处理系统。     

Signal Integrity: Fault Modeling and Testing in High-Speed SoCs

As we approach 100 nm technology the interconnect issues are becoming one of the main concerns in the testing of gigahertz system-on-chips. Voltage distortion (noise) and delay violations (skew) contribute to the signal integrity loss and ultimately functional error, performance degradation and reliability problems. In this paper, we first define a model for integrity faults on the high-speed interconnects. Then, we present a BIST-based test methodology that includes two special cells to detect and measure noise and skew occurring on the interconnects of the gigahertz system-on-chips. Using an inexpensive test architecture the integrity information accumulated by these special cells can be scanned out for final test and reliability analysis.     

Characterization and optimization of copper chemical mechanical planarization

The feature scale planarization of the copper chemical mechanical planarization (CMP) process has been characterized for two copper processes using Hitachi 430-TU/Hitachi T605 and Cabot 5001/Arch Cu10K consumables. The first process is an example of an abrasive-free polish with a high-selectivity barrier slurry, while the second is an example of a conventional abrasive slurry with a low-selectivity barrier slurry. Copper fill planarization has been characterized for structures with conformal deposition as well as with bumps resulting from bottom-up fill. Dishing and erosion were characterized for several structures after clearing. The abrasive-free polish resulted in low sensitivity to overpolish and low saturation levels for dishing and erosion. Consequently, this demonstrated superior performance when compared to the International Technology Roadmap for Semiconductors (ITRS) 2000 roadmap targets for planarization. While the conventional slurry could achieve the 0.13-μm technology node requirements, the abrasive-free polish met the planarization requirements beyond the 0.10-μm technology node.     

环境友好阻燃环氧树脂覆铜板研究进展

论述了环境友好阻燃环氧树脂覆铜板研究开发的意义。提出通过开发并使用含氮、磷或硅的非卤阻燃型环氧树脂,含磷、氮或磷-氮的功能性阻燃固化剂和在体系中添加有机磷阻燃剂、氢氧化铝等无机阻燃剂等途径来开发环境友好阻燃环氧树脂覆铜板。并对我国在今后该领域的研究作了展望。     

A novel compact circuit for 4-PAM energy-efficient high speed interconnect data transmission and reception

Transmission of signals, whether on-chip or off-chip, places severe constraints on timing and extracts a large price in energy. New silicon device technologies, such as back-plane CMOS, provide a programmable and adaptable threshold voltage as an additional tool that can be used for low power design. We show that one particularly desirable use of this freedom is energy-efficient high-speed transmission across long interconnects using multi-valued encoding. Our multi-valued CMOS circuits take advantage of the threshold voltage control of the transistors, by using the signal-voltage-to-threshold-voltage span, in order to make area-efficient implementations of 4-PAM (pulse amplitude modulation) transceivers operating at high speed. In a comparison of a variety of published technologies, for signal transmission with interconnects of 10-15 mm length, we show up to 50% improvement in energy for on-chip signal transmission over binary encoding together with higher limits for operating speeds without a penalty in circuit noise margin.