检测实验室如何开展管理评审工作

详细论述了管理评审的基本概念、如何开展管理评审工作以及中国实验室国家认可委员会的有关政策。     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

C-Testable modified-Booth multipliers

In this paper the testability of modified-Booth array multipliers for standard cells based design environments is examined for first time. In such cases the structure of the cells may be unknown, thus Cell Fault Model (CFM) is adopted. Two C-testable designs are proposed. A design for an N _x × N_y bits modified-Booth multiplier, which uses ripple carry addition at the last stage of the multiplication, is first proposed. The design requires the addition of only one extra primary input and 38 test vectors with respect to CFM. A second C-testable design is given using carry lookahead addition at the last stage which is the case of practical implementations of modified-Booth multipliers. Such a C-testable design using carry lookahead addition is for first time proposed in the open literature. This second design requires the addition of 4 extra primary inputs. One-level and two-levels carry lookahead adders, are considered. The C-testable design requires 61 test vectors for the former and 73 test vectors for the latter, respectively. The hardware and delay overheads imposed by both C-testable designs are very small and decrease when the size of the multiplier increases.     

基于修正ANT逻辑高速树形32 Bit Carry Lookahead加法器

一种用修正全NMOS管逻辑（ANT）实现的树形结构高速32bit carry Lookahead加法器,使用两相时钟动态CMOS逻辑、修正不反向ANT逻辑和二进制树形结构实现。该加法器运用0．25μm工艺,文中给出了修正ANT逻辑中所有晶体管的宽长尺寸和仿真结果,最高工作频率为2GHz。计算结果在3．5个时钟周期后有效。     

家用插头插座的单一化研究

分析了家用插头插座使用中存在的问题,结合国外产品的使用情况,提出家用插头插座单一化的优点及其发展趋势,并论证了技术上的可行性。     

对称三进制光学加法器的进位直达通道设计

以对称三进制光学半加器为基础,提出了一个对称三进制光学全加器方案。主要介绍了进位直达并行通道在对称三进制光学全加器中的实现方案和工作原理,从而论证了实现对称三进制光学全加器的可行性。     

用于DDS系统相位累加器的加法器设计

直接数字频率合成器(DDS)具有频率转换时间短、分辨率高、输出相位连续等优点,是现代频率合成的重要技术之一。在分析了DDS基本原理的基础上,对DDS中的核心单元之一相位累加器进行了系统研究。分别利用镜像电路和超前进位全加器实现信号源累加器模块,进行模拟仿真并比较,结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。     

性能改进的16位超前进位加法器

加法运算是最重要最基本的运算,所有的其他基本算术运算,减、乘、除、模乘运算最终都能归结为加法运算。在不同的场合使用的加法器对其要求也不同,有的要求速度更快,有的要求面积更小。基于速度更快的要求,对3种常用加法器从结构与性能上进行比较,给出了综合面积与速度的比较。进而对超前进位加法器进行了进一步改进,加入了流水线结构设计,大大提高了其速度性能。     

温室气体清单编制的思路和基本原则

文章简要介绍了企业建立温室气体排放清单的编制思路和基本原则。文章通过分析编制温室气体清单时如何确定编制范围,关键排放源,计算原理与方法,排放因子和活动强度,以及清单质量保证的注意事项,作者提出了组织（企业）建立温室气体排放清单的建议。     

“数字信号处理”中重叠保留法的证明

重叠保留法是计算一个短序列与一个无限长序列线性卷积的有效方法。就我们所知，多数《数字信号处理》教材详细叙述了重叠保留法的步骤，有些教材还从线性卷积与循环卷积的关系出发给出了重叠保留法的原理，笔者认为这种解释不够清楚、也不够严谨。本文给出了一个较为严谨而准确的证明。