电化学电容-电压法表征等离子体掺杂超浅结

采用电化学电容-电压(ECV)法对等离子体掺杂制备的Si超浅p n结进行了电学表征.通过对超浅p n结样品ECV测试和二次离子质谱(SIMS)测试及比较,发现用ECV测试获得的p 层杂质浓度分布及结深与SIMS测试结果具有良好的一致性,但ECV测试下层轻掺杂n型衬底杂质浓度受上层高浓度掺杂影响很大.ECV测试具有良好的可控性与重复性.对不同退火方法等离子体掺杂形成的超浅结样品的ECV系列测试结果表明,ECV能可靠地表征结深达10nm,杂质浓度达1021cm-3量级的Si超浅结样品,其深度分辨率可达纳米量级,它有望在亚65nm节点CMOS器件的超浅结表征中获得应用.     

用肖特基电容电压特性数值模拟法确定调制掺杂AlxGa1-xN/GaN异质结中的极化电荷

研究发展了用肖特基电容电压特性数值模拟确定调制掺杂Al_xGa_1-xN/GaN异质结中极化电荷的方法.在调制掺杂的Al_0.22Ga_0.78N/GaN异质结上制备了Pt肖特基接触,并对其进行了C-V测量.采用三维费米模型对调制掺杂的Al_0.22Ga_0.78N/GaN异质结上肖特基接触的C-V特性进行了数值模拟,分析了改变样品参数对C-V特性的影响.利用改变极化电荷、n-AlGaN 关键词： xGa_1-xN/GaN异质结')" href="#">Al_xGa_1-xN/GaN异质结 极化电荷 电容电压特性 数值模拟     

肖特基结的制备与势垒测量

采用磁控溅射方法在Nb07％-SrTiO3基片上制作Au薄膜接触,并在氧气气氛下750℃退火30 min,在室温环境下测量电流电压和电容电压等特性曲线,观测整流特性,根据相应实验数据采用饱和电流法、电容C-2与反偏电压V成线性关系计算肖特基势垒的大小.     

Development of a triangular-plate MEMS tunable capacitor with linear capacitance-voltage response

This paper introduces a modified structure for parallel-plate-based MEMS tunable capacitors. The capacitor has triangular electrodes with geometric and structural asymmetry, which enhances its performance. The device structure is also equipped with a set of cantilever beams between capacitor’s electrodes, called middle beams. These beams provide extra stiffness as tuning voltage increases and delay the pull-in which results in a higher tunability. They also reduce the high sensitivity of the capacitance to the voltage change and linearize the C-V response. An analytical model is developed to optimize the capacitor’s dimensions for maximum linearity of the response. Numerical simulations demonstrate tunabilities over 150% where more than 2/3 of which is highly linear. Capacitors fabricated with PolyMUMPs verify that the design technique proposed in this paper can improve the linearity of the device and increase the maximum tunability. The proposed design has a simple geometry and is fabricated using three structural layers, and therefore, it can be easily integrated in tunable filters or other RF circuits.     

Influence of bias-temperature stressing on the electrical characteristics of SiOC:H film with Cu/TaN/Ta-gated capacitor

Experiments on bias-temperature stressing, capacitance-voltage measurements, current-voltage characteristics, and time-dependent dielectric breakdown were performed to evaluate the reliability of Cu and low-k SiOC:H integration. A high leakage current of ∼8 × 10⁻¹⁰ to 2 × 10⁻⁸ A/cm² at 1 MV/cm in SiOC:H dielectrics in a Cu-gated capacitor, and a lower 2 × 10⁻¹⁰ to 5 × 10⁻¹⁰ A/cm² at 1 MV/cm in a Cu/TaN/Ta-gated capacitor, were observed at evaluated temperatures. The drift mobility of the Cu⁺ ions in the Cu/TaN/Ta-gated capacitor was lower than that in a Cu-gated capacitor. A physical model was developed to explain the observed kinetics of Cu⁺ ions that drift in Cu-gated and Cu/TaN/Ta-gated capacitors. The electric field in the Cu-gated MIS capacitor in the cathode region is believed to be increased by the accumulation of positive Cu⁺ ions, which determines the breakdown acceleration. Good Cu⁺ ions drift barrier layers are required as reliable interconnects using thin TaN and Ta layers. Additionally, Schottky emission dominates at low electric fields, E<1.25 MV/cm, and Poole-Frenkel emission dominates at high fields, E>1.5 MV/cm.     

基于锗硅异质纳米晶的非易失浮栅存储器的存储特性

利用自组织生长和选择化学刻蚀方法在超薄SiO2隧穿氧化层上制备了渐变锗硅异质纳米晶,并通过电容.电压特性和电容-时间特性研究了该纳米结构浮栅存储器的存储特性.测试结果表明,该异质纳米晶非易失浮栅存储器具有良好的空穴存储特性,这是由于渐变锗硅异质纳米晶中Ge的价带高于Si的价带形成了复合势垒,空穴有效地存储在复合势垒的Ge的一侧.     

Temperature dependent electrical characteristics of Sn/p-Si Schottky diodes

Current-voltage and capacitance-voltage characteristics of Sn/p-Si Schottky diodes measured in the temperature range 80-320 K are presented and analysed. Anomalous strong temperature dependencies of the ideality factor and apparent barrier height were obtained. There was also a considerable difference between the apparent barrier heights obtained from current-voltage and capacitance-voltage characteristics. These anomalies are explained by the domination of the current by a high level of thermionic-field emission, and by the presence of deep levels near the Sn/Si interface, which yield a reduction of free hole concentration and a significant temperature dependence of the charge stored near the metal-semiconductor (MS) interface. The evaluation of temperature dependence of forward current for thermionic-field emission resulted in the following parameters: characteristic energy E₀₀ = 9.8 meV, Schottky barrier height at zero bias Φ_b0 = 0.802 eV, bias coefficient of barrier height β = 0, and effective Richardson constant A* = 37.32 A cm⁻² K⁻².     

Effect of alumina thickness on Al_2O_3/InP interface with post deposition annealing in oxygen ambient

In this paper, the effect of alumina thickness on Al2O3/InP interface with post deposition annealing （PDA） in the oxygen ambient is studied. Atomic layer deposited （ALD） Al2O3 films with four different thickness values （5 nm, 7 nm, 9 nm, 11 rim） are deposited on InP substrates. The capacitance-voltage （C-V） measurement shows a negative correlation between the alumina thickness and the frequency dispersion. The X-ray photoelectronspectroscopy （XPS） data present significant growth of indium-phosphorus oxide near the Al2O3/InP interface, which indicates serious oxidation of InP during the oxygen annealing. The hysteresis curve shows an optimum thickness of 7 nm after PDA in an oxygen ambient at 500 ℃ for 10 min. It is demonstrated that both sides of the interface are impacted by oxygen during post deposition annealing. It is suggested that the final state of the interface is of reduced positively charged defects on Al2O3 side and oxidized InP, which degrades the interface.     

TiN and TaN diffusion barriers in copper interconnect technology: Towards a consistent testing methodology

The present status of work on diffussion barriers for copper in multilevel interconnects is surveyed briefly, with particular emphasis on TiN and TaN, and silicon dioxide as the interlayer dielectric. New results are presented for these materials, combining thermal annealing and bias temperature stress testing. With both stress methods, various testing conditions are compared using capacitance-vs-voltage (C-V) and leakage current-vs-voltage (I-V) measurements to characterize the stressed samples. From an evaluation of these data and a comparison with other testing approaches, conditions for a consistent testing methodology of barrier reliability are outlined.     

用肖特基电容电压特性数值模拟法确定调制掺杂Al_xGa_(1-x)N/GaN异质结中的极化电荷

研究发展了用肖特基电容 电压特性数值模拟确定调制掺杂AlxGa1 -xN GaN异质结中极化电荷的方法 .在调制掺杂的Al0 2 2 Ga0 78N GaN异质结上制备了Pt肖特基接触 ,并对其进行了C V测量 .采用三维费米模型对调制掺杂的Al0 2 2 Ga0 78N GaN异质结上肖特基接触的C V特性进行了数值模拟 ,分析了改变样品参数对C V特性的影响 .利用改变极化电荷、n AlGaN层掺杂浓度和肖特基势垒高度对C V曲线不同部分位置和形状影响不同 ,可以精确地求取极化电荷面密度 .通过模拟 ,得到Al0 2 2 Ga0 78N厚度为 45nm的调制掺杂Al0 2 2 Ga0 78N GaN异质结界面附近极化电荷面密度为 6 78× 10 1 2 cm- 2 .