Chiral phase transition and equation of state in chiral imbalance

The chiral phase transition and equation of state are studied within a novel self-consistent mean-field approximation of the two-flavor Nambu-Jona-Lasinio model. In this newly developed model, modifications to the chemical μ and chiral chemical \begin{document}$\mu_5$\end{document} potentials are naturally included by introducing vector and axial-vector channels from Fierz-transformed Lagrangian to the standard Lagrangian. In the proper-time scheme, the chiral phase transition is a crossover in the \begin{document}$T-\mu$\end{document} plane. However, when \begin{document}$\mu_5$\end{document} is incorporated, our study demonstrates that a first order phase transition may emerge. Furthermore, the chiral imbalance will soften the equation of state of quark matter. The mass-radius relationship and tidal deformability of quark stars are calculated. The maximum mass and radius decrease as \begin{document}$\mu_5$\end{document} increases. Our study also indicates that the vector and axial-vector channels exhibit an opposite influence on the equation of state.     

论携号转网行为的私法规制

以电信用户入网协议为切入点,电信用户的携号转网行为应受到《合同法》《消费者权益保护法》等私法规范的保护与限制。该行为引起的格式条款解释、合同终止、违约责任、损失赔偿等问题,不能仅靠《电信条例》等公法规范来调整。应当积极引导广大消费者用户以私法领域相关规定为依据,转变争议解决思维,拓宽纠纷处理途径,合理选择维权手段,以保护自身合法民事权益,与行业监管部门共同推动电信行业有序发展。     

无线传感器网络中移动sink节点的路径规划

在无线传感器网络中,大量感知数据汇集到sink节点的采集方法会导致sink节点附近的节点能量耗尽,造成能量空洞。针对该问题,利用移动的sink节点进行数据收集是一种解决方法,其中移动sink的路径规划成为一个重要的问题。提出了一个移动sink路径规划算法,将无线传感器中随机分布的节点划分为不同的子区域,寻找sink节点移动的最佳转向点,最终得到最优的移动路径,以实现无线传感器网络生命周期最大化。仿真实验表明,与现有方案相比,该算法能显著延长网络的生命周期。     

基于时空的弱点状运动目标检测技术

如何在复杂背景下持续有效地检测目标位置,一直是研究者们需要面对的主要挑战。本文在研究红外点状移动目标特征的基础上,根据目标无纹理,无形状的特性,提出一种改进的形态学目标增强算法,并利用目标连续时空不变性检测目标。首先,建立多尺度的图像金字塔,在每层上采用改进的形态学算法快速、粗糙定位小目标。然后进一步的根据目标在时空上的位置相关性,提出基于目标运动特征分析的精确检测方法。得到精确稳定的检测结果。最后实验结果表明与经典的形态学检测算法及其他算法相比,该技术能更有效地检测弱小目标,具有更高的鲁棒性。     

Spectral estimates for saddle point matrices arising in weak constraint four‐dimensional variational data assimilation

We consider the large sparse symmetric linear systems of equations that arise in the solution of weak constraint four‐dimensional variational data assimilation, a method of high interest for numerical weather prediction. These systems can be written as saddle point systems with a 3 × 3 block structure but block eliminations can be performed to reduce them to saddle point systems with a 2 × 2 block structure, or further to symmetric positive definite systems. In this article, we analyse how sensitive the spectra of these matrices are to the number of observations of the underlying dynamical system. We also obtain bounds on the eigenvalues of the matrices. Numerical experiments are used to confirm the theoretical analysis and bounds.     

腔光子-自旋波量子耦合系统中各向异性奇异点的实验研究

通过耦合三维微波腔中光子和腔内钇铁石榴石单晶小球中的自旋波量子形成腔-自旋波量子的耦合系统,并通过精确调节系统参数在该实验系统中观测到各向异性奇异点.奇异点对应于非厄米系统中一种特殊状态,在奇异点处,耦合系统的本征值和本征矢均简并,并且往往伴随着非平庸的物理性质.以往大量研究主要集中在各向同性奇异点的范畴,它的特征是在系统参数空间中沿着不同参数坐标趋近该奇异点时具有相同的函数关系.在这篇文章中,主要介绍实验上在腔光子-自旋波量子耦合系统中通过调节系统的耦合强度和腔的耗散衰减系数两条趋近奇异点的路径而实现了各向异性奇异点,具体分别对应于在趋近奇异点时,本征值的虚部的变化与耦合强度和腔的衰减系数的变化会有线性和平方根不同的行为.各向异性奇异点的实现有助于基于腔光子-自旋波量子耦合系统的量子信息处理和精密探测器件的进一步研究.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.