Monochromatic sinks in nearly transitive arc-colored tournaments

Let T be the set of all arc-colored tournaments, with any number of colors, that contain no rainbow 3-cycles, i.e., no 3-cycles whose three arcs are colored with three distinct colors. We prove that if T∈T and if each strong component of T is a single vertex or isomorphic to an upset tournament, then T contains a monochromatic sink. We also prove that if T∈T and T contains a vertex x such that T−x is transitive, then T contains a monochromatic sink. The latter result is best possible in the sense that, for each n≥5, there exists an n-tournament T such that (T−x)−y is transitive for some two distinct vertices x and y in T, and T can be arc-colored with five colors such that T∈T, but T contains no monochromatic sink.     

SOI CMOS SRAM单元单粒子翻转效应的模拟

为简单快速模拟静态随机存储器(SRAM)的单粒子效应,在二维器件数值模拟的基础上,以经典的双指数模型为原型,通过数值拟合得到了单粒子效应瞬态电流脉冲的表达式,考虑晶体管偏压对瞬态电流的影响,得到修正的瞬态电流表达式,将其带入电路模拟软件HSPICE中进行SRAM存储单元单粒子翻转效应的电路模拟,通过与实际单粒子实验结果的对比,验证了这种模拟方法的实用性。     

CMOS存储器瞬时辐照效应规律实验研究

对超深亚微米存储器(32 k SRAM)激光辐照下的剂量率效应进行了初步研究,实验测量了SRAM激光辐照下的效应规律,比较了零时SRAM的状态(读状态和片选无效状态)对效应规律的影响,得到了一些初步的效应规律.     

中子引起单粒子翻转过程的Monte Carlo计算模拟

从中子与硅原子相互作用的物理机理出发,利用Monte Carlo方法编制了中子引起单粒子翻转的计算模拟程序,并对14 MeV中子环境下的16K位静态存储器硅片翻转过程中的物理量进行了计算,同时可为中子引起的单粒子翻转的研究提供截面和描述内部物理过程的参考数据。     

New techniques for efficiently assessing reliability of SOCs

In this paper we propose an approach to speed-up Fault Injection campaigns for the evaluation of dependability properties of complex digital systems. The approach exploits FPGA devices for system emulation, and new techniques are described, allowing emulating the effects of faults and to observe faulty behavior. Thanks to its flexibility and efficiency, the approach is suitable to be applied to SOC devices. The paper points out the flexibility of the approach, able to inject different faults of different types in custom logic, memory blocks, and processor cores. The proposed approach combines the speed of hardware-based techniques, and the flexibility of simulation-based techniques. Experimental results are provided showing that speed-up figures of up to 3 orders of magnitude with respect to state-of-the-art simulation-based techniques can be achieved.     

EEPROM和SRAM瞬时剂量率效应比较

对一种256 kb EEPROM电路AT28C256和一种256 kb SRAM电路HM62256开展了"强光一号"瞬时剂量率效应实验,测量了存储器的闩锁效应、翻转效应等。HM62256的翻转阈值为9.0×106 Gy(Si)/s,闩锁阈值高于5.4×107 Gy(Si)/s。AT28C256的闩锁阈值为2×107 Gy(Si)/s,存储单元翻转阈值高于3.0×108 Gy(Si)/s。对于SRAM,其翻转阈值远低于闩锁阈值;而对于EEPROM,在瞬时辐照下,闩锁阈值远低于存储单元的翻转阈值。基于两种存储器的数据存储原理,分析了SRAM和EEPROM瞬时剂量率效应差异的原因。     

An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing

With fabrication technology reaching nano levels, systems are exposed to higher susceptibility to soft errors. Thus, development of effective techniques for designing soft error tolerant systems is of high importance. In this work, an integrated soft error tolerance technique based on logical implications and transistor sizing is proposed. In order to reduce implication learning time, a set of source and target nodes with predefined thresholds are selected and implications between these nodes are extracted. Then, the impact of adding a functionally redundant wire (FRW) due to each implication is evaluated. This is done based on identifying an implication path and the gates along the implication path whose detection probabilities will be reduced due to adding the implication FRW. Then, the gain of an implication is estimated in terms of reduction in fault detection probabilities of gates along an implication path. The implication with the highest gain is selected. The process is repeated until the gain is less than a predetermined threshold. The proposed implication-based fault tolerance technique enhances the circuit reliability with minimal area overhead based on enhancing logical masking. However, its effectiveness depends on the existence of such relations in a circuit and can enhance circuit reliability upto a certain level. To enhance circuit reliability to any required level, selective-transistor redundancy (STR) based technique is then applied. This technique is based on providing fault tolerance for individual transistors with high detection probability based on transistor duplication and sizing. Experimental results show that the proposed integrated fault tolerance technique achieves similar reliability in comparison to applying STR alone with lower area overhead.     

Hybrid time and hardware redundancy to mitigate SEU effects on SRAM-FPGAs: Case study over the MicroLAN protocol

SRAM-based field programmable gate arrays (FPGAs) are particularly sensitive to single event upsets caused by high-energy space radiation. Single Event Upset (In order to successfully deploy the SRAM-FPGA based designs in aerospace applications, designers need to adopt suitable hardening techniques. In this paper, we describe novel hybrid time and hardware redundancy (HT&HR) structures to mitigate SEU effects on FPGA, especially digital circuits that are designed with bidirectional ports. The proposed structures that combine time and hardware redundancy decrease the SEU propagation mechanisms among the redundant hard units. Analysis results and fault injection experiments on some standard ISCAS benchmarks and MicroLAN protocol, as a case study over the bidirectional ports, show that the capability of tolerating SEU effects in HT&HR technique increases up to 70 times with respect to solely hardware redundant versions. On average, the proposed method provides 39.2 times improvement against single upset faults and 14.9 times for double upset faults; however it imposes about 14.7% area overhead. Also, for the considered benchmarks, HT&HR circuits become 8.8% faster on the average than their TMR versions.     

一种单粒子翻转机制及其解决方法

针对某款超深亚微米专用集成电路(ASIC)出现的异常单粒子翻转现象,分析了导致异常翻转的机制,针对这种机制提出了2种解决方法,并给出了2种解决方法的适用范围。重离子试验结果表明,采用新方法实现的时序逻辑具备更高的翻转阈值和更低的翻转截面,基于新方法研制的ASIC产品的抗单粒子翻转能力得到显著提高。     

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

This paper presents UA²TPG, a static analysis tool for the untestability proof and automatic test pattern generation for SEUs in the configuration memory of SRAM-based FPGA systems. The tool is based on the model-checking verification technique. An accurate fault model for both logic components and routing structures is adopted. Experimental results show that many circuits have a significant number of untestable faults, and their detection enables more efficient test pattern generation and on-line testing. The tool is mainly intended to support on-line testing of critical components in FPGA fault-tolerant systems.