A novel mechanical diced trench structure for warpage reduction in wafer level packaging process

The wafer warpage problem, mainly originated from coefficient of thermal expansion mismatch between the materials, becomes serious in wafer level packaging as large diameter wafer is adopted currently. The warpage poses threats to wafer handling, process qualities, and can also lead to serious reliability problems. In this paper, a novel mechanical diced trench structure was proposed to reduce the final wafer warpage. Deep patterned trenches with a depth about 100 μm were fabricated in the Si substrate by mechanical dicing method. Both experiment and simulation approaches were used to investigate the effect of the trenches on the wafer warpage and the influence of the geometry of the trenches was also studied. The results indicate that, by forming deep trenches, the stress on the individual die is decoupled and the total wafer warpage could be reduced. The final wafer warpage is closely related to the trench depth and die width. Trenched sample with a depth of 100 μm can decrease the wafer warpage by 51.4%.     

CPU电源电路用沟槽棚MOSFET与e-JFET开关管的功耗对比研究

本文主要针对低压功率开关管的功耗进行了理论分析，并在此基础上分别对两种典型结构槽栅MOSFET和e-JFET在不同工作频率 下的功耗分布和总功耗进行了定量的仿真计算和对比。通过研究发现，在一定工作条件下，常闭型e-JFET比目前常用的沟槽栅型MOSFET仅开关功耗就降低约24%，总功耗则降低约30%，将其运用于CPU电源电路中的开关功率管的制造，在高频领域有着极好的应用前景。     

SiGe-collector trench gate insulated gate bipolar transistor fabricated using multiple target sputtering

A new type of trench gate IGBT (insulated gate bipolar transistor) which uses a SiGe layer for the collector is experimentally investigated. SiGe collectors with different Ge content are deposited by multiple cathode sputtering making low temperature processing possible. The change in turn-off characteristics with Ge content is also investigated. Results indicate that the use of a SiGe collector reduces the tail current at turn-off due to the reduced injection of holes to the n⁻ drift region.     

Optimum design for minimum on-resistance of low voltage trench power MOSFET

An optimum trench width for the minimum on-resistance of a trench MOSFET (T-MOS) is determined analytically with the resistance contribution from the accumulation layer taken into account. Inclusion of the accumulation resistance is shown to be indispensable to the on-resistance of the T-MOS especially for a relatively large value of the trench width. The analytical results show a fair agreement with the numerical simulations using ATLAS.     

Power Trench MOSFETs with very low specific on-resistance for 25V applications

In this paper, an investigation of the benefits of deep ultra violet lithography for the manufacturing of Trench MOSFETs and its impact on device performance is presented. We discuss experimental results for devices with a pitch size down to 0.6 μm fabricated with an unconventional implant topology and a simplified manufacturing scheme. The fabricated Trench MOSFETs are benchmarked against previously published TrenchMOS technologies by de-embedding the parasitic substrate resistance, revealing a record-low specific on-resistance of 5.3 mΩ mm² at a breakdown voltage of 30 V (V_gs = 10 V).     

大马士革镶嵌结构对Cu膜微结构及应力的影响

通过TEM、SEM、XRD和EBSD,观察了Cu互连线和平坦Cu膜的微观结构。采用薄膜应力测试分布仪和二维面探测器XRD,测量了平坦Cu膜和Cu互连线的应力,计算了Cu薄膜热应力的理论值。凹槽侧壁成为互连线新的形核区域,并且在平行于侧壁的方向形成较弱的(111)织构。与平坦膜相比,互连线晶粒尺寸明显变小(、111)织构较弱,且存在大量Σ3和Σ9晶界。平坦膜和互连线分别表现出压应力和张应力。降温过程产生的热应力为互连线的主要应力。     

Breakdown voltage improvement of LDMOSs by charge balancing: An inserted P-layer in trench oxide (IPT-LDMOS)

For the first time, the novel inserted P-layer in trench oxide of LDMOS structure (IPT-LDMOS) is proposed in which a trench oxide with inserted P-layer is considered in the drift region to improve the breakdown voltage. Our simulation with two dimensional ALTAS simulator shows that by determining the optimum doping concentration of the P-layer, the charges of the N-drift and P-layer regions would be balanced. Therefore, complete depletion at the breakdown voltage in the drift region happens. Also, electric field in the IPT-LDMOS is modified by producing additional peaks which decrease the common peaks near the drain and source junctions.     

用于MEMS的硅湿法深槽刻蚀技术研究

针对用于MEMS的硅湿法深槽刻蚀技术,对KOH腐蚀液的配方、掩蔽技术等关键技术进行了研究,获得了优化的KOH腐蚀条件;利用该技术,成功地刻蚀出深度高达315μm、保护区域完好的深槽。为硅基MEMS体加工获得微机械结构提供了一个好方法。     

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5 mΩ mm², respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5 V.     

Stress-induced trench narrowing in Cu interconnect of sub-20 nm node: FEM simulation

The trench narrowing at sub-20 nm BEOL process has been reproduced using a FEM simulation. The trench narrowing can be observed under the conditions of both the high intrinsic stress of a hard mask and the specific design of metal line patterns with the length difference between center and side trenches. As the center trench length increases, a trench displacement takes place because trench walls have a high compressive stress gradient from the side trench surface to the center one in the direction parallel to the trench lines. The displacement also decreases with decreasing the width of the trench while increasing with decreasing the width of the low-k wall. The high pattern density of metal or dummy lines around the trenches decreases the displacement of the low-k dielectric walls. Considering the distribution of pattern densities at left and right sides of the trenches, a symmetrical pattern density deforms the trench wall more largely than an asymmetrical one. Young's modulus of SiOCH is not a sensitive factor on the trench narrowing. Our displacement analysis may be used in predicting hot spots of void defects in the Cu interconnect of real Si wafers.