Phase transition in the one-dimensional pair-hopping model with unusual one-electron hopping

By modifying the conventional one-electron hopping behavior, we study effects of an occupation-dependent hopping on the ground state of the half-filled one-dimensional pair-hopping model. At weak coupling, the use of bosonization and renormalization-group analysis techniques helps to derive the phase diagram. Such unusual hopping is shown to drive a spin-gap transition and to introduce a new region where the triplet superconducting instability dominates for positively small pair-hopping interaction.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

几种涉密网主机系统保护及审计技术的比较

论文比较详细地阐述了涉密网主机系统所面临的安全隐患,提出了涉密网主机安全防护所要解决的几个技术问题,并就可能实现的技术方法进行了探讨和比较。     

国产风机盘管空调系统常见问题分析

分析了国产风机盘管使用中常见的问题,指出机组因风量不足、冷量风量匹配不合理以及风机盘管某些设备故障,导致了风机盘管精度低、舒适性差、能耗高等一系列问题。指出应引起空调设计和运行维护人员的注意。     

构建高扩展性的县级广电宽带数据网络

提出在县市级广电宽带数据网络的建设过程中,要着眼业务发展,突出高扩展性,构建基于标准、扩展灵活的主干网,实现网络建设的可持续性发展,并结合实际,从核心设备、端口、中继带宽、网络业务4个方面对扩展能力进行了阐述.     

宽带DDS跳频源设计

直接数字合成（DDS）简单可靠、控制方便，具有很高的频率分辨率，高速转换，非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后，提出宽带跳频源设计方案。     

一个基于PE分层技术的电子政务网络平台

电子政务网络建设的主要目标就是建立一个开放的、基于标准的统一网络平台，并在该平台上实现政府不同部门之间的信息交换和资源共享，同时保证各部门信息的独立和安全。通过介绍电子政务网络建设中的主流技术——MPLSVPN，提出了一种基于该技术原理的PE分层技术，详细讨论了基于该分层技术的电子政务网络平台的实现过程和主要技术，并对其性能参数进行了测试与分析。     

医用激光治疗机的触摸屏控制系统设计

介绍了医用红宝石激光器触摸屏控制系统的基本结构，分析了医用红宝石激光器中主要电磁干扰（EMI）的产生机制，提出了具体的电磁兼容（EMC）技术措施并得到实验验证。