可调色散补偿技术及其在DWDM系统中的应用

文章对可调色散补偿(TDC)的几种主要实现方式进行了介绍,并对这几种实现方式进行了对比,详细描述了TDC模块在密集波分复用(DWMD)系统中各种不同场合的应用,给出了相关的应用模型,最后总结了TDC技术在DWMD系统应用中的发展目标.     

氢氟酸和PSG牺牲层腐蚀的TDC模型

对不同结构,即直沟道结构、冒泡结构和组合沟道结构的氢氟酸牺牲层腐蚀进行了研究.以往的牺牲层腐蚀模型和实验结果不能很好地吻合.以往的模型和实验结果的误差随着腐蚀时间的增加而增大.本文提出了一个修正模型,在修正模型中：HF的扩散系数是浓度和温度的函数;腐蚀速率常数是温度的函数;此外还考虑了腐蚀产物对腐蚀过程的影响.对于组合沟道结构,对腐蚀前端形状的描述采用了一个新的数学模型.实验结果和以往的模型以及修正模型进行了对比,结果表明修正模型能够和实验结果吻合得很好.     

基于DTC技术的静止卫星通信抗干扰性能

TDC(Transform Domain Communication变换域通信)技术采用的是躲避式抗干扰方式.在通信中实施干扰躲避,可以有效地避免或降低干扰对通信的影响.文中首先对TDC技术进行了简要介绍,对这一抗干扰技术应用于静止卫星通信系统的可行性和应用方式进行了探讨.仿真表明基于TDC技术的静止卫星通信系统具有抗多种干扰的能力,但由于通信时延,在干扰频率发生变化时,通信的抗干扰能力有所下降.     

TOT measurement implemented in FPGA TDC

Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays(FPGAs), FPGA time-to-digital converters(TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold(TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity.This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method,TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15 ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates.     

高分辨率时间数字转换电路的PLD实现

高分辨率时间数字转换系统(TDC)采用环形延时门单元(RGDS)高分辨率系统,在可编程器件(PLD)上实现,解决了延时门的综合、延时时间的离散性等问题.由于设计、实现和集成电路工艺无关,所以可以方便地移植到其他系统和PLD芯片中.本设计在Altera公司的CPLD芯片上的仿真测试表明,时间分辨率最高可达3.5ns.本实验通过了时序仿真和硬件测试.     

A true random number generator based on the photon arrival time registered in a coincidence window between two single-photon counting modules

True random number generators are essential components for communications to be confidentially secured. In this paper a new method is proposed to generate random sequences of numbers based on the difference of the arrival times of photons detected in a coincidence window between two single-photon counting modules.     

PET成像前端读出芯片研究进展

在过去的半个多世纪里,虽然正电子发射断层(PET)成像设备在外型上没有多大变化,但在技术和方法上发生了多次革命性的飞跃。微电子技术在PET成像领域的应用将进一步推动PET向更小体积、更高性能、更低成本等方向发展。从PET系统成像原理出发,详细综述了PET前端读出芯片技术的研究进展。将PET探测器信号的前端读出和信号处理分为光电转换、信号采集、脉冲高度分析、峰值探测和保持、信号数字化和数字信号处理等环节,给出了各个环节的微电子电路实现。然后,描述了PET前端读出大规模专用集成电路的研发进展,指出采用数字电路的方法来处理探测器前端读出和模拟信号处理已经成为PET前端电子的发展趋势,而且集成PET专用DSP的多通道智能前端读出电路已经成为一个重要的方向。     

TDC‐GP21在时差法超声波流量计中的应用

为了实现高精度的流量测量,设计了一种基于 TDC‐GP21的时差法超声波流量计.系统以 MSP430单片机为核心,选用高精度时间间隔测量芯片 TDC‐GP21,有效的解决了时差法超声波流量计中高精度时差测量的问题.文中详细介绍了时间间隔测量芯片 TDC‐GP21的功能模块及工作流程,设计了一种超声波回波信号处理电路,并对超声波流量计系统硬件电路与软件方案进行了阐述.实验表明,系统的最大测量误差在±1%以内,达到了准确度等级为1级的要求.     

基于延时锁定环的时间数字转换器设计

A time-to-digital converter(TDC) based on a reset-free and anti-harmonic delay-locked loop(DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid "false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 m CMOS technology, and its core area occupies 0.7 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than 0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.