基于DSP的智能电源控制单元设计与实现

本文利用TI公司TMS320F28335芯片高效的浮点运算能力,结合片上丰富的外设,设计并实现了一种具有高可靠性的智能电源控制单元。该控制单元周期性地对各片上外设进行自检维护,完成多路负载通道控制、电压、电流的实时监控,并对故障进行指示、处理和上报,同时提供人机交互界面更新状态信息。经过验证,该控制单元工作稳定,具备良好的工程应用价值。     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

面向应用的无线传感器网络

结合具体的应用环境分析了无线传感器网络发展到第二阶段需要考虑的重点问题；探讨了基于上述应用需求的无线传感器网络的协议栈结构和今后的研究方向。     

Joint scheduling and power control supporting multicasting in wireless ad hoc networks

This paper addresses the problem of power control in a multihop wireless network supporting multicast traffic. We face the problem of forwarding packet traffic to multicast group members while meeting constraints on the signal-to-interference-plus-noise ratio (SINR) at the intended receivers. First, we present a distributed algorithm which, given the set of multicast senders and their corresponding receivers, provides an optimal solution when it exists, which minimizes the total transmit power. When no optimal solution can be found for the given set of multicast senders and receivers, we introduce a distributed, joint scheduling and power control algorithm which eliminates the weak connections and tries to maximize the number of successful multicast transmissions. The algorithm allows the other senders to solve the power control problem and minimize the total transmit power. We show that our distributed algorithm converges to the optimal solution when it exists, and performs close to centralized, heuristic algorithms that have been proposed to address the joint scheduling and power control problem.     

一种用于三电平逆变器的SVPWM调制方法研究

本文从二极管箝位型三电平逆变器的基本结构出发，分析其输出状态，推导出六角形空间电压矢量图。然后从一种改进的，可以减小开关损耗，避免高的dv／dt三电平空间矢量PWM调制策略出发，建立了基于Matlab的详细仿真方案，验证了方案的可行性。文章给出了扇区判断的算法流程图，脉冲生成模块的内部结构图，其中的扇区判断的算法和脉冲生成方法对于用DSP实现三电平SVPWM具有重要的参考价值。     

A profit-maximizing supply chain network design model with demand choice flexibility

We present a profit-maximizing supply chain design model in which a company has flexibility in determining which customers to serve. The company may lose a customer to competition if the price it charges is too high. We show the problem formulation and solution algorithm, and discuss computational results.     

CONCEPTUAL DESIGN STUDIES OF AN 84 GHz, 500 kW, CW GYROTRON

The feasibility of an 84 GHz, 500 kW, CW gyrotron for ECRH on an experimental tokamak will be presented in this paper. Mode competition and mode selection procedures are carefully investigated by considering various candidate modes and the TE_10,4 mode is chosen as the operating mode. A conventional cylindrical cavity resonator with weak input and output tapers and parabolic roundings is considered for interaction studies. Self-consistent, both single mode and time-dependent, calculations are carried out and power and efficiencies are computed for a typical set of beam parameters. The results show that an output power of well over 500 kW, CW and efficiency around 40% can be reached without a depressed collector.     

一种900-MHz 20-mW CMOS功率放大器的设计

提出了一个工作电压为3V，工作频率900MHZ，输出功率为20mW的高效率CMOS功率放大器。为了达到设计目标，文章采用了一些特殊的方法，包括三级放大结构，级间的调谐匹配和层叠差分结构。     

On a class of new and practical performance indexes for approximation of fold bifurcations of nonlinear power flow equations

Efficient measurement of the performance index (the distance of a loading parameter from the voltage collapse point) is one of the key problems in power system operations and planning and such an index indicates the severity of a power system with regard to voltage collapse. There exist many interesting methods and ideas to compute this index. However, some successful methods are not yet mathematically justified while other mathematically sound methods are often proposed directly based on the bifurcation theory and they require the initial stationary state to be too close to the unknown turning point to make the underlying methods practical.This paper first gives a survey of several popular methods for estimating the fold bifurcation point including the continuation methods, bifurcation methods and the test function methods (Seydel's direct solution methods, the tangent vector methods and the reduced Jacobian method) and discuss their relative advantages and problems. Test functions are usually based on scaling of the determinant of the Jacobian matrix and it is generally not clear how to determine the behaviour of such functions. As the underlying nonlinear equations are of a particular type, this allows us to do a new analysis of the determinants of the Jacobian and its submatrices in this paper. Following the analysis, we demonstrate how to construct a class of test functions with a predictable analytical behaviour so that a suitable index can be produced. Finally, examples of two test functions from this class are proposed. For several standard IEEE test systems, promising numerical results have been achieved.