Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

微流控分析芯片制作中的低温键合技术

微流控分析芯片制作方法的研究是微流控分析的基础。制作性能良好的微流控分析芯片时,基片与盖片的键合技术十分重要。本文针对近年来发展迅速的低温键合技术,对各种方法进行了评价,并对其发展前景进行了展望。     

The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs

Modular testing is an attractive approach to testing large system ICs, especially if they are built from pre-designed reusable embedded cores. This paper describes an automated modular test development approach. The basis of this approach is that a core or module test is dissected into a test protocol and a test pattern list. A test protocol describes in detail how to apply one test pattern to the core, while abstracting from the specific test pattern stimulus and response values. Subsequent automation tasks, such as the expansion from core-level tests to system-chip-level tests and test scheduling, all work on test protocols, thereby greatly reducing the amount of compute time and data involved. Finally, an SOC-level test is assembled from the expanded and scheduled test protocols and the (so far untouched) test patterns. This paper describes and formalizes the notion of test protocols and the algorithms for test protocol expansion and scheduling. A running example is featured throughout the paper. We also elaborate on the industrial usage of the concepts described.     

一种RISC单片机的分块结构寄存器堆

介绍了一种用于ＲＩＳＣ单片机ＰＩＣ１６Ｃ５７的寄存器堆，讨论了为降低功耗所采用的分块结构，详细说明了译码逻辑、ＳＲＡＭ单元、读／写电路和文件选择寄存器等电路的形式及其工作原理     

一种低压低功耗SRAM/SOI单元设计

提出一种改进4管自体偏压结构SRAM/SOI单元.基于TSUPREM4和MEDICI软件的模拟和结构性能的分析,设计单元结构并选取结构参数.该结构采用nMOS栅下的含p+埋沟的衬底体电阻代替传统6管CMOSSRAM单元中的pMOS元件,具有面积小、工艺简单的优点.该结构可以在0.5V的电源电压下正常工作,与6管单元相比,该单元瞬态响应正常,功耗只有6管单元的1/10,满足低压低功耗的要求.     

Composite poly(dimethylsiloxane)/glass microfluidic system with an immobilized enzymatic particle-bed reactor and sequential sample injection for chemiluminescence determinations

A three-layer poly(dimethylsiloxane) (PDMS)/glass microfluidic system for performing on-chip solid-phase enzymatic reaction and chemiluminescence (CL) reaction was used for the determination of glucose as a model analyte. A novel method for the immobilization of controlled-pore-glass based reactive particles on PDMS microreactor beds was developed, producing an on-chip solid-phase reactor that featured large reactive surface and low flow impedance. Efficient mixing of reagent/sample/carrier streams was achieved by incorporating chaotic mixer structures in the microfluidic channels. A conventional sequential injection (SI) system was adapted for direct coupling with the microfluidic system, and combined with hydrostatic delivery of reagents to achieve efficient and reproducible sample introduction at 10 μl levels. A detection limit of 10 μM glucose (3σ), and a precision of 3.1% RSD (n=7, 0.2 mM glucose) were obtained using the SI-microfluidic-CL system integrated with a glucose oxidase (GOD) reactor. Carryover was <5% at a throughput of 20 samples/h.     

Subtle gate oxide defect elimination to improve the reliability of a 32M-bit SRAM product

Tiny defects may escape from in-line defect scan and pass WAT (Wafer Acceptance Test), CP (Chip Probing), FT (Final Test) and SLT (System Level Test). Chips with such kind of defects will cause reliability problem and impact revenue significantly. It is important to catch the defects and derive the prevention strategy earlier in the technology development stage. In this paper, we investigate an SRAM with tiny defects which passed in-line defect scan, WAT, CP and FT but failed in HTOL (High Temperature Operation Life) test, one of the product reliability qualification items. FA (Failure Analysis) reveals gate oxide missing defect is the root cause. The goal is to pass reliability qualification and release product into production on schedule. The failure mechanism, optimization of gate oxide process, enhancement of defect scan and testing methodology will be introduced. Experiment results show very good HTOL performance by the combination of process and testing optimization.     

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Single event multiple-cell upsets (MCU) increase sharply with the semiconductor devices scaling. The impacts of several test factors on heavy ion single event MCU in 65 nm SRAM are studied based on the buildup of MCU test data acquiring and processing technique, including the heavy ion LET, the tilt angle, the device orientation, the test pattern and the supply voltage; the MCU physical bitmaps are extracted correspondingly. The dependencies of parameters such as the MCU percentage, MCU mean and topological pattern on these factors are summarized and analyzed. This work is meaningful for developing a more reasonable single event test method and assessing the effectiveness of anti-MCU strategies on nanometer-scale devices.     

A novel stability and process sensitivity driven model for optimal sized FinFET based SRAM

Technology enhancement has increased sensitivity of process variations of scaled SRAM on the verge of instability. This demands a process variation (PV) aware stability model for the modern SRAM. This paper first analyzes PV severity on readability, writability and static leakage current and provides a statistical model. The paper further improves the proposed model by using curve fitting method for stability modeling and modified Least Mean Square with first order differentiation to extract best fitting parameters. The resulting model exhibits characteristics of standard current voltage equation based model. A evolutionary optimization technique is proposed to achieve optimal cell dimension for process tolerant SRAM. The resulting SRAM is tested for worst case stability analysis using Gaussian distribution based statistical approach. Simulation results show that the resulting optimized SRAM improves read, standby and word line write margins by 4%, 4% and 23%, respectively.