High sensitivity chemiluminescence enzyme immunoassay for detecting staphylococcal enterotoxin A in multi-matrices

In this study, detection of staphylococcal enterotoxin A (SEA) in multi-matrices using a highly sensitive and specific microplate chemiluminescence enzyme immunoassay (CLEIA) has been established. A pair of monoclonal antibodies (mAbs) was selected from 37 anti-SEA mAbs by pairwise analysis, and the experimental conditions of the CLEIA were optimized. This CLEIA exhibited high performance with a wide dynamic range from 6.4 pg mL⁻¹ to 1600 pg mL⁻¹, and the measured low limit of detection (LOD) was 3.2 pg mL⁻¹. No cross-reactivity was observed when this method was applied to test SEB, SEC1, and SED. It has also been successfully applied for analyzing SEA in a variety of environmental, biological, and clinical matrices, such as sewage, tap water, river water, roast beef, peanut butter, cured ham, 10% nonfat dry milk, milk, orange juice, human urine, and serum. Thus, the highly sensitive and SEA-specific CLEIA should make it attractive for quantifying SEA in public health and diagnosis in near future.     

1.25 G光纤收发器SFP设计与仿真

对千兆SFP光纤收发器中控制电路参数设计及利用Cadence软件进行仿真展开了一定的探讨,提出千兆SFP光纤收发器中控制电路设计方案,分析了光发射模块和接收模块的性能,主要研究了在Cadence互连设计软件平台中,利用高速电路设计和信号完整性的理论,采用仿真分析的方法,对千兆SFP光收发模块进行板级分析设计,并对接收部分MAX3748芯片的SPICE模型的I/O口、MAX3744与MAX3748接口、SFP光收发模块布线进行了仿真分析,从而使电路性能达到最优化.     

基于AM41V4传感器的高清高速CMOS相机系统设计

为满足国防、科研及工业中快速变化场景拍摄时,更高帧频、更大分辨率的要求,研发了一款高清高速相机。该文介绍了高分辨率高帧频CMOS图像传感器芯片AM41V4的功能与特点,并基于该芯片设计了一套高分辨率高帧频的相机系统,该系统使用FPGA作为整个系统的时序控制核心,以DDR动态存储器作为成像暂存器,可以依据试验场合的具体拍摄要求实现灵活多变的工作模式。相机系统在图像分辨率为1 920×1 080时帧频可达1 000fps,并具有实时监视功能。该系统具有拍摄速度快、成像清晰、高性能、灵活性好等优点,适用于高速运动目标的快速捕获与拍摄记录。     

Explicit constructions of separating hash families from algebraic curves over finite fields

Let X be a set of order n and Y be a set of order m. An (n,m,{w ₁, w ₂})-separating hash family is a set of N functions from X to Y such that for any with , |X ₁| = w ₁ and |X ₂| = w ₂, there exists an element such that . In this paper, we provide explicit constructions of separating hash families using algebraic curves over finite fields. In particular, applying the Garcia–Stichtenoth curves, we obtain an infinite class of explicitly constructed (n,m,{w ₁,w ₂})–separating hash families with for fixed m, w ₁, and w ₂. Similar results for strong separating hash families are also obtained. As consequences of our main results, we present explicit constructions of infinite classes of frameproof codes, secure frameproof codes and identifiable parent property codes with length where n is the size of the codes. In fact, all the above explicit constructions of hash families and codes provide the best asymptotic behavior achieving the bound , which substantially improve the results in [ 8, 15, 17] give an answer to the fifth open problem presented in [11].     

一种基于SFP封装的数字可调光衰减器的实现

研制了一种基于SFP（Small Form-factor Pluggable）封装的数字可调光衰减器（VOA）模块。该可调光衰减器模块集成了微电子机械系统（MEMS）式的可调光衰减器（VOA）和精密电控制单元,采用标准的SFP封装和接口,实现小型化可插拔,高精度数字化衰减功能。该VOA不仅具有SFP器件特有的高集成度和灵活配置等特点,支持热插拔和即插即用,同时还具有MEMS光衰减器固有的反应速度快、线性度好、高稳定性、高衰减等光学性能,因此在光网络通信设备和光传输系统中具有广泛的应用前景。     

A fast automatic power control circuit for a small form-factor pluggable laser diode drive

A fast automatic power control (APC) circuit for a laser diode driver (LDD) has been implemented in a 0.6-μm BiCMOS process. The APC circuit adopts double-loops and variable-bandwidth techniques to achieve a turn-on time of < 400 μs for most kinds of TOSAs. Thus, it meets the small form-factor pluggable (SFP) agreement. Such techniques make a good tradeoffbetween stability, accuracy, turn-on time, noise and convenience. The measured results indicate that the APC circuit is suitable for SFP LDD.     

Design of 4.25 Gbps Small Form-factor Pluggable(SFP) Transceiver

Compact, hot-pluggable, and data-agnostic, SFP modules bring up to 4.25 Gbps to a flexible new form factor. The SFP transceiver which is the core device of optical communication is always the research focus in the field of optical communication for both telecommunication and data communication applications. The working principles of SFP including the transmitter components, the receiver components and the microcontroller are discussed in detail. The basic theory of high-speed signal and the concept of high - speed circuit, high-speed board design techniques are presented. A new design of high performance, cost effective SFP transceiver and PCB layout are also presented. The performance of the transceiver is analyzed and the characteristics of the sample are coincident with the expected ones. The status of the transceiver can be monitored and controlled by I2C bus through the interface in real time. This transceiver can meet the requirement of SFF-8472.     

一种多功能SFP光模块监测平台的设计与实现

设计并实现了-种SFP光模块实时监测平台,该平台可实时监测SFP光模块的温度、电压、激光器偏置电流以及发射和接收光功率等参量.该平台的应用简化了系统维护工作,提高了系统的可靠性.     

RZ-DPSK光信号新型解调系统的设计与实现

设计并实现了一种RZ-DPSK光信号解调系统。该系统采用廉价的SFP+光模块替代昂贵的平衡接收机进行信号的光电转换,并设计了数字平衡检测算法对延迟干涉仪进行动态调整,以找到其最佳工作点降低系统的误码率。     

千兆SFP光纤收发器中控制电路参数的设计与仿真

本文提出千兆SFP光纤收发器中控制电路参数的设计方案,就千兆SFP光纤收发器中的控制电路展开了探讨,并对接收部分SPICE模型的I/O口进行了仿真分析。