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基于FPGA乘法器架构的RNS与有符号二进制量转换 总被引:1,自引:1,他引:0
RNS(余数数制系统)是一种整数运算系统,在粒度精确性,能源损耗和响应速度上有很大的优势.从RNS到二进制数的输入输出转换是基于余数算法的专用架构实现的关键.本文提出了一个基于N类模的RNS与有符号二进制量的通用转换算法在FPGAs的乘法器上的实现过程.该算法能更有效地进行有符号数与RNS的转换.基于该算法类型乘法器在同类型乘法器中显示出了速度优势.文章中该架构被映射到Altera的10K系列的FPGA上. 相似文献
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Javier Ramírez Uwe Meyer-Bäse Fred Taylor Antonio García Antonio Lloris 《The Journal of VLSI Signal Processing》2003,34(3):227-237
The design of high performance, high precision, real-time digital signal processing (DSP) systems, such as those associated with wavelet signal processing, is a challenging problem. This paper reports on the innovative use of the residue number system (RNS) for implementing high-end wavelet filter banks. The disclosed system uses an enhanced index-transformation defined over Galois fields to efficiently support different wavelet filter instantiations without adding any extra cost or additional look-up tables (LUT). A selection of a small wordwidth modulus set are the keys for attaining low-complexity and high-throughput. An exhaustive comparison against existing two's complement (2C) designs for different custom IC technologies was carried out. Results reveal a performance improvement of up to 100% for high-precision RNS-based systems. These structures demonstrated to be well suited for field programmable logic (FPL) assimilation as well as for CBIC (cell-based integrated circuit) technologies. 相似文献
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Scaling is an important operation because of the iterative nature of arithmetic processes in digital signal processors (DSPs). In residue number system (RNS)–based DSPs, scaling represents a performance bottleneck based on the complexity of inter‐modulo operations. To design an efficient RNS scaler for special moduli sets, a body of literature has been dedicated to the study of the well‐known moduli sets {2n ? 1, 2n, 2n + 1} and {2n, 2n ? 1, 2n+1 ? 1}, and their extension in vertical or horizontal forms. In this study, we propose an efficient programmable RNS scaler for the arithmetic‐friendly moduli set {2n+p, 2n ? 1, 2n+1 ? 1}. The proposed algorithm yields high speed and energy‐efficient realization of an RNS programmable scaler based on the effective exploitation of the mixed‐radix representation, parallelism, and a hardware sharing technique. Experimental results obtained for a 130 nm CMOS ASIC technology demonstrate the superiority of the proposed programmable scaler compared to the only available and highly effective hybrid programmable scaler for an identical moduli set. The proposed scaler provides 43.28% less power consumption, 33.27% faster execution, and 28.55% more area saving on average compared to the hybrid programmable scaler. 相似文献
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Marisa Freitas 《Analytica chimica acta》2009,649(1):8-8272
Neutrophils, also known as polymorphonuclear leukocytes (PMN), are the most common type of white blood cells, comprising about 50-70% of all white blood cells. In the event of inflammatory processes, neutrophils display increased mobility, tissue influx ability, prolonged life span, and an increased phagocytic capacity, constituting the initial participants in the cellular defense of the organism. One of the most important defense systems of neutrophils corresponds to their ability to mediate a strong oxidative burst through the formation of reactive oxygen species (ROS) and reactive nitrogen species (RNS). While oxidative burst is important for the elimination of invading microorganisms, the overproduction of ROS and RNS or the impairment of endogenous antioxidant defenses may result to detrimental effects to the host. The nature and the extent of ROS and RNS production by neutrophils in response to different stimuli is, consequently, a matter of extensive research, with scientific reports showing an enormous variability on the detection methodologies employed. This review attempts to provide a critical assessment of the most common approaches to identify and quantify reactive species formed during the neutrophils’ oxidative burst. The detection mechanisms and performance, as well as advantages and limitations of the different methodologies, are scrutinized, focusing on the use of fluorimetric, chemiluminometric and colorimetric probes. 相似文献
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以{2n-1,2n,2n+1,2n-1-1,2n+1-1}为余数基,在余数系统(RNS)的基础上设计了一种128抽头有限脉冲响应(FIR)滤波器。针对大位宽输入,利用基于华莱士(Wallace)树结构的纯组合逻辑电路,实现了二进制到余数的转换。相较于一般抽头中乘法器级联加法器的结构,设计的乘累加(MAC)单元将加法运算合并到部分积求和中,减少了一级模加法器,使得电路延时进一步减少。此外,通过对进位保留加法器(CSA)的中间结果取模,避免了加法运算引起的位宽增加,从而降低了整个运算的复杂度。电路在FPGA上设计实现。实验结果表明,该滤波器的延时为3.55 ns,功耗为2 585 mW,消耗的硬件资源明显降低。 相似文献
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Comparison is a difficult operation in residue number systems (RNS). Besides the straightforward comparison of binary equivalents of RNS numbers, shortcut methods for moduli-set τ={2n−1, 2n, 2n+1} have been proposed that only slightly improve the corresponding figures of merit. On the other hand, we have encountered only one hardware realization of 4-moduli RNS comparison, where the corresponding moduli-set does not include any power-of-two modulo. In this paper, we examine and provide shortcut RNS comparators for three moduli-sets with four modulus, all containing τ as a subset. Evaluation results show 15–136% speed-up and 39–366% less energy in comparison to the straightforward reverse-and-compare comparators. 相似文献
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利用RNS(余数数制系统)可以执行并行的数据处理以及实现快速无进位算法,在VLSI(超大规模集成电路)设计中表现出低功耗、占用面积小和时延少等优良特性.根据中国剩余定理,基于(2n-1)2n(2n+1)模组,利用Verilog语言设计了RNS到位数据流的数值转换接口电路.以使传统的多位数(Bit)的复杂运算转化为多个并行的较少位数的简单运算,从而降低单次运算的复杂度、时延和功耗.该转换电路面向"Σ-Δ"编码的数据流,不同于传统的二进制数据转换,可以方便地与基于DSD(Direct Stream Digital)的Delta-Sigma系统进行无缝连接. 相似文献
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