嵌入式RISC核MPEG2/AC3解码器

介绍了在一个嵌入RISC核的AC3／MPEG2音／视频解码器中，通过增加特殊指令及其相应的硬件逻辑，对AC3的音频解码进行了一定的改进，不仅达到了AC3解码的实时性要求，而且降低了对存储器的要求。     

一种RISC单片机的分块结构寄存器堆

介绍了一种用于ＲＩＳＣ单片机ＰＩＣ１６Ｃ５７的寄存器堆，讨论了为降低功耗所采用的分块结构，详细说明了译码逻辑、ＳＲＡＭ单元、读／写电路和文件选择寄存器等电路的形式及其工作原理     

32位RISC结构体系的性能优势

在计算机技术的许多变革中,最有意义的是从复杂指令集计算机(CISC)过渡到精简指令集计算机(R ISC)体系结构的转变。正是R ISC的出现发展大大推动了嵌入式系统性能的提高和功能的完善。文中以嵌入式32位R ISC结构体系中最有代表性的ARM为例,从精简指令集的概念、指令集的简洁高效性、寻址空间、运算和数据处理能力和对操作系统的支持等方面,详细论述了32位R ISC体系结构的性能优势。     

32位RISC微处理器"龙腾R2"浮点流水线的设计和实现

文章介绍了32位RISC微处理器“龙腾R2”浮点处理单元的体系结构和设计，重点讨论了乱序执行、乱序、结束的高性能浮点流水线设计。为了实现流水线中的精确中断响应，本文采用了一种基于操作数指数和操作类型的浮点异常预测的方法．根据预测结果决定流水线的发射策略。基于0．18μm标准单元综合的结果表明：采用该方法实现的浮点处理流水线．与顺序控制和基于Tomasub算法实现的浮点处理单元相比，整个FPU在付出较少硬件面积的情况下得到了理想的效果．满足功能和时序要求。     

A rapid turnaround design of a high speed VLSI search processor

Performance of relational database systems is a major impediment to their use in many applications. We have designed and implemented a customized RISC processor to accelerate associative search and aggregation operations for relational database systems. Since the processor is programmable and supports many queries concurrently, a system utilizing tens of such processors is capable of handling thousands of complex search requests simultaneously.

While the design of a VLSI programmable processor is a complex process, research prototyping requires a fast turnaround design process. We took advantage of the logic programming paradigm and the silicon compiler technology to explore and simulate architecture alternatives prior to the actual implementation. The prototyping process allowed us to complete the chip design in nine months. The resulting processor, fabricated in 2 Itm CMOS technology, consists of 91,000 transistors, executes over 18 million predicate evaluations per second, and searches database contents at 74 megabytes per second.     

MD16:基于特定RISC规则的16位DSP处理器

为达到最佳的应用性价比,一个重要思想就是把RISC和DSP的优点融合在一个平台上,但是目前这方面工作侧重以RISC结构为基础构建RISC-DSP混合型处理器。与此对比,本文提出了一种以DSP为基础并辅以若干RISC特性的处理器构造思想。这种思想表现在体系结构设计上为采用局部类RISC同质寄存器结构来优化指令编码、采用基于二维扩展LAOD/STORE寻址机制来增强寻址能力;表现在微结构设计上为采用类RISC四级流水线来降低控制、数据相关性,同时由于基于寄存器的运算操作和扩展的LOAD/STORE寻址操作功能正交,因此又可采用指令内并行机制来提高运行效率。芯片采用SMIC 0.18μm6层CMOS工艺加工,在核心电压1.8V情况下,其可工作在0～162MHz,此时功耗为1.1mW/MHz。     

基于ARM的射频识别读卡器电路设计

针对ISO14443,ISO15693和Tag-it等多种协议,提出了一种新型的基于高级RISC微处理器（ARM）的射频识别系列通用射频卡读卡器的电路设计,并使用加密模块实现了在操作过程中对数据流的加密。介绍了系统组成、工作原理和工作流程,给出了加密电路和射频网络的详细硬件设计,对该设计结果进行了测试及分析,结果表明该电路能对有效范围内的多种类型的卡准确无误地读写和加密。     

网络处理器--下一代网络发展的核心技术

阐述了网络处理器的概念及其产生的技术背景，并给出了网络处理器的基本结构，同时指出其优点。     

Tailoring Extremely Narrow FWHM in Hypsochromic and Bathochromic Shift of Polycyclo-Heteraborin MR-TADF Materials for High-Performance OLEDs

Developing double boron-based emitters with extremely narrow band spectrum and high efficiency in organic light-emitting diodes (OLEDs) is crucial and challenging. Herein, we report two materials, NO-DBMR and Cz-DBMR , hinge on polycyclic heteraborin skeletons based on role-play of the highest occupied molecular orbital (HOMO) energy levels. The NO-DBMR contains an oxygen atom, whereas the Cz-DBMR has a carbazole core in the double boron-embedded ν-DABNA structure. The synthesized materials resulted in an unsymmetrical pattern for NO-DBMR and surprisingly a symmetrical pattern for Cz-DBMR . Consequently, both materials showed extremely narrow full width at half maximum (FWHM) of 14 nm in hypsochromic (pure blue) and bathochromic (Bluish green) shifted emission without losing their high color fidelity. Furthermore, both materials show high photoluminescence quantum yield (PLQY) of over 82 %, and an extremely small singlet-triplet energy gap (ΔE_ST) of 0.04 eV, resulting in high reverse intersystem crossing process (k_RISC) of 10⁵ s⁻¹. Due to the efficient thermally activated delayed fluorescence (TADF) characteristics, the fabricated OLEDs based on these heteraborins manifested maximum external quantum efficiency (EQE_max) of 33.7 and 29.8 % for NO-DBMR and Cz-DBMR , respectively. This is the first work reported with this type of strategy for achieving an extremely narrow emission spectrum in hypsochromic and bathochromic shifted emissions with a similar molecular skeleton.     

基于S12X系列双核单片机的CAN网关设计

集成XGATE协处理器内核的S12XE系列双核单片机具有处理速度快、反应时间短、功耗低等优点,在嵌入式应用中具有独特优势和很好的应用前景。本文采用16位双核单片机MC9S12XEQ512作为主控制器,以集成信号和电源隔离功能的CAN收发器芯片ADM3053来实现CAN接口电路,设计并实现了一个可以连接3个CAN通信子网的CAN网关,有效实现了系统的小型化、低功耗、低成本。采用双核处理技术来优化CAN网关的处理流程,由协处理器XGATE来处理各种中断,S12X主CPU则专注于协议处理和消息转发。实际应用表明,系统运行稳定可靠,与传统的采用单处理器实现的CAN网关相比,系统的数据吞吐能力和实时性得到了明显改善。