基于误差估值累加开环校正的诱导式欺骗检测方法

诱导式卫星欺骗干扰可诱导航空器逐渐偏离预定航迹，难以被发现，因此及时有效地检测干扰是飞行安全的保障。在现有紧组合导航体制基础上，设计了一种基于误差估值累加开环校正的紧组合导航结构，并证明了其性能与传统闭环校正紧组合导航性能等效。在此结构中，将紧组合导航系统与自适应序贯概率比检测方法结合，提出了一种基于误差估值累加开环校正的诱导式欺骗检测方法，融合紧组合导航信息与其他不受欺骗影响的导航信息，构建欺骗检测统计量进行诱导式欺骗检测。仿真结果表明，开环校正结构可避免随时间累加的惯性导航系统误差所导致的组合导航滤波器发散问题，同时欺骗检测方法可进一步提高算法对“最坏”情形下微小诱导式欺骗的检测效果。     

一款紧凑增强型可变阻抗电磁带隙结构

基于传统AI-EBG结构,提出了一种小尺寸的增强型电磁带隙结构,实现了从0.5~9.4 GHz的宽频带-40 dB噪声抑制深度,且下截止频率减少到数百MHz,可有效抑制多层PCB板间地弹噪声。文中同时研究了EBG结构在高速电路应用时的信号完整性问题,使用差分信号方案可改善信号完整性。     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

RF磁控溅射制备钛酸锶钡BST纳米薄膜

钛酸锶钡(BST)薄膜作为一种高K介质材料在微电子和微机电系统等领域具有广阔的应用前景,人们已对BST薄膜的制备工艺技术和介电性能进行了大量的研究。BST纳米薄膜的制备工艺直接影响和决定着薄膜的介电性能(介电常数、漏电流密度、介电强度等)。对RF磁控反应溅射制备BST纳米薄膜的工艺技术进行了综述。从溅射靶的制备、溅射工艺参数的优化、热处理、薄膜组分的控制,及制备工艺对介电性能的影响等方面,对现有研究成果进行了较全面的总结。     

软件集成测试技术研究

首先分析了集成测试的原理和特点，并指出了集成测试的重要性。然后结合传统软件与面向对象软件开发的方法和技术，详细介绍了传统软件的集成测试方法和策略，并深入分析了面向对象软件集成测试的原理和方法。     

异构数据集成方法研究与实现

为解决异构数据集成的复杂性问题，文章提出了一种异构数据同步的新方法——半集成式中间件法。该方法成功地应用在重庆市社会保障综合信息系统中，具有易于实现、可扩展性、跨平台性和效率高等特点。     

采用RF2607的WLAN自动增益控制设计

介绍了宽动态变化范围的新型可变增益放大器RF2607的特性、功能,给出了利用RF2607设计无线局域网(WLAN)通信中自动增益控制部分的实用电路.     

宽工作电压范围单电源CMOS误差放大器

采用0.8μm标准数字CMOS工艺(VTN0=0.836V,VTP0=0.930V),设计并流片验证了具有宽工作电压范围(3～6V),可作SOC系统动态电源管理芯片内部误差放大器应用的单电源CMOS运算放大器。该误差放大器芯核同时具有适合低电压工作,并对工艺参数变化不敏感的优点。对于相同的负载情况,在3V的工作电压下,开环电压增益AD=83.1dB,单位增益带宽GB=2.4MHz,相位裕量Φ=85.2°,电源抑制比PSRR=154.0dB,转换速率Sr=2.2V/μs;在6V工作电压下,AD=85.1dB,GB=2.4MHz,Φ=85.4°,PSRR=145.3dB,Sr=3.4V/μs。