基于DSP的智能电源控制单元设计与实现

本文利用TI公司TMS320F28335芯片高效的浮点运算能力,结合片上丰富的外设,设计并实现了一种具有高可靠性的智能电源控制单元。该控制单元周期性地对各片上外设进行自检维护,完成多路负载通道控制、电压、电流的实时监控,并对故障进行指示、处理和上报,同时提供人机交互界面更新状态信息。经过验证,该控制单元工作稳定,具备良好的工程应用价值。     

High-voltage and low specific on-resistance power UMOSFET using P and N type columns

For the first time, we present the unique features exhibited by power 4H–SiC UMOSFET in which N and P type columns (NPC) in the drift region are incorporated to improve the breakdown voltage, the specific on-resistance, and the total lateral cell pitch. The P-type column creates a potential barrier in the drift region of the proposed structure for increasing the breakdown voltage and the N-type column reduces the specific on-resistance. Also, the JFET effects reduce and so the total lateral cell pitch will decrease. In the NPC-UMOSFET, the electric field crowding reduces due to the created potential barrier by the NPC regions and causes more uniform electric field distribution in the structure. Using two dimensional simulations, the breakdown voltage and the specific on-resistance of the proposed structure are investigated for the columns parameters in comparison with a conventional UMOSFET (C-UMOSFET) and an accumulation layer UMOSFET (AL-UMOSFET) structures. For the NPC-UMOSFET with 10 µm drift region length the maximum breakdown voltage of 1274 V is obtained, while at the same drift region length, the maximum breakdown voltages of the C-UMOSFET and the AL-UMOSFET structures are 534 and 703 V, respectively. Moreover, the proposed structure exhibits a superior specific on-resistance (R_on,sp) of 2 mΩ cm², which shows that the on-resistance of the optimized NPC-UMOSFET are decreased by 56% and 58% in comparison with the C-UMOSFET and the AL-UMOSFET, respectively.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.     

Small‐Sized High‐Power PIN Diode Switch with Defected Ground Structure for Wireless Broadband Internet

This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns.     

宽带DDS跳频源设计

直接数字合成（DDS）简单可靠、控制方便，具有很高的频率分辨率，高速转换，非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后，提出宽带跳频源设计方案。     

一个基于PE分层技术的电子政务网络平台

电子政务网络建设的主要目标就是建立一个开放的、基于标准的统一网络平台，并在该平台上实现政府不同部门之间的信息交换和资源共享，同时保证各部门信息的独立和安全。通过介绍电子政务网络建设中的主流技术——MPLSVPN，提出了一种基于该技术原理的PE分层技术，详细讨论了基于该分层技术的电子政务网络平台的实现过程和主要技术，并对其性能参数进行了测试与分析。     

面向应用的无线传感器网络

结合具体的应用环境分析了无线传感器网络发展到第二阶段需要考虑的重点问题；探讨了基于上述应用需求的无线传感器网络的协议栈结构和今后的研究方向。     

Joint scheduling and power control supporting multicasting in wireless ad hoc networks

This paper addresses the problem of power control in a multihop wireless network supporting multicast traffic. We face the problem of forwarding packet traffic to multicast group members while meeting constraints on the signal-to-interference-plus-noise ratio (SINR) at the intended receivers. First, we present a distributed algorithm which, given the set of multicast senders and their corresponding receivers, provides an optimal solution when it exists, which minimizes the total transmit power. When no optimal solution can be found for the given set of multicast senders and receivers, we introduce a distributed, joint scheduling and power control algorithm which eliminates the weak connections and tries to maximize the number of successful multicast transmissions. The algorithm allows the other senders to solve the power control problem and minimize the total transmit power. We show that our distributed algorithm converges to the optimal solution when it exists, and performs close to centralized, heuristic algorithms that have been proposed to address the joint scheduling and power control problem.     

医用激光治疗机的触摸屏控制系统设计

介绍了医用红宝石激光器触摸屏控制系统的基本结构，分析了医用红宝石激光器中主要电磁干扰（EMI）的产生机制，提出了具体的电磁兼容（EMC）技术措施并得到实验验证。     

城域波分网络中的光环路保护分析

介绍了在城域波分网络中应用的四种环形保护倒换方案及其实现方式，并对各种保护倒换方案的特性进行了分析比较。