Effective identification of dominant fully absorbing sets for Raptor-like LDPC codes

The error-rate floor of low-density parity-check (LDPC) codes is attributed to the trapping sets of their Tanner graphs. Among them, fully absorbing sets dominantly affect the error-rate performance, especially for short blocklengths. Efficient methods to identify the dominant trapping sets of LDPC codes were thoroughly researched as exhaustively searching them is NP-hard. However, the existing methods are ineffective for Raptor-like LDPC codes, which have many types of trapping sets. An effective method to identify dominant fully absorbing sets of Raptor-like LDPC codes is proposed. The search space of the proposed algorithm is optimized into the Tanner subgraphs of the codes to afford time-efficiency and search-effectiveness. For 5G New Radio (NR) base graph (BG) 2 LDPC codes for short blocklengths, the proposed algorithm finds more dominant fully absorbing sets within one seventh of the computation time of the existing search algorithm, and its search-effectiveness is verified using importance sampling. The proposed method is also applied to 5G NR BG1 LDPC code and Advanced Television Systems Committee 3.0 type A LDPC code for large blocklengths.     

运载火箭时序仿真测试系统设计

检测运载火箭地面测试设备的方法种类繁多,方法复杂,测试周期较长。设计一种运载火箭时序仿真测试系统,采用FPGA芯片的SOPC(可编程片上系统)技术,基于全双工USB 3.0控制芯片( CYUSB3014)完成上位机通信,单板模拟运载火箭飞行过程中64路时序系统发出的时序信号和时串信号,对不同测试需求的地面测试设备进行功能检测和故障诊断。具有方法简单,通用性好、精度等级高、通道数多的优点,能有效提高地面测试设备在测试任务中的测试效率。     

新一代运载火箭时序仿真系统信号完整性分析

新一代运载火箭时序仿真系统具有数字电路速度快、集成度高的特点,系统要求发出多路高精度时序、时串信号以满足新一代运载火箭地面测试设备的检查与校准需求,因此信号完整性问题在系统设计中不容忽视。针对仿真系统的典型模块(USB 3.0 Super-speed差分线、FPGA外设数据走线、时钟走线)进行建模分析仿真得出PCB硬件电路设计参数,给出时序仿真系统设计信号完整性问题的抑制和解决方法,优化了板级信号质量,改善系统可靠性、工作连续性和输出精度,可有效提高新一代运载火箭测试效率和测试可靠性。     

基于USB3.0 主模式高速接口卡设计

针对现行USB2.0接口已不能满足现代大容量数据高速度传输需求,提出一种基于USB3.0和FPGA的高速传输的解决方案。该方案通过配置可编程接口把EZ-USB FX3设置成master主模式,优化DMA数据传输通道,实现了电脑与接口卡之间数据高速传输。文章详细地介绍如何提高传输速度的方法,经实际传输测试,该接口卡能在传输速率高达350Mbyte/s依然能保持正确无误的高速传输。     

用于SCA ASIC测试的数字读出模块设计

高速开关电容阵列(SCA)具有高速采样、低功耗的特点,基于SCA的高速波形数字化是目前高精度时间测量的一个重要研究方向。为此,我们开展SCA芯片的研究,目前已设计完成原型ASIC设计,并正在进行后续版本的改进设计。为便于未来多版本ASIC的测试和评估,需设计具有一定通用性的数字读出模块,本论文工作主要介绍此模块的设计工作以及相应的数据读出软件。数字读出模块基于FPGA实现对待测ASIC的控制、配置及数据读出,采用DDR3片外存储芯片,使用USB3.0等接口进行数据传输;上位机软件基于Python3.7设计,实现了数据采集与波形绘制等功能。目前已使用设计完成的数字读出模块对第2版SCA ASIC进行了初步的测试,测试结果表明,此读出模块工作正常,且SCA芯片输出结果符合预期。     

结合模板与互信息的全景图拼接技术研究与实现

针对传统互信息图像配准拼接算法计算量大、效率低等问题,本文结合模板匹配,提出基于模板与互信息的全景图拼接技术。首先将误差法和二次匹配误差法相结合,对待拼接图像进行初次模板匹配,划定大致重叠区域;接着从互信息量的角度比较相邻重叠的两幅图像的相似性,通过建立两幅图像之间的互信息量,计算最大互信息,获得匹配区域;然后再次利用模板匹配,设定最佳匹配区域,最终实现图像配准拼接。在VS2010+Opencv环境中编程实现重叠图像的拼接,并验证了算法的正确性。实验表明,本文算法具有计算量相对小,自动化程度高,配准拼接精度高等优点。     

Sn-3.0Ag-0.5Cu真空再流焊工艺技术研究

为了获得低热阻和解决不同焊接材料之间的热应力匹配问题,大功率DC-DC模块电源产品广泛采用了载体组件作为功率元器件热沉的散热方法。载体组件由金属基板和陶瓷基板焊接而成,为了得到无空洞的焊接界面,载体组件采用了真空再流焊工艺技术。文中从焊料形态、焊接表面处理、真空度等几个方面介绍了载体组件的Sn-3.0Ag-0.5Cu真...     

ADSP Tiger SHARC 101S在基于最小二乘恒模算法中的应用

对ADSP Tiger SHARC 101S的在最小二乘恒模算法中的应用进行了研究。首先介绍了最小二乘恒模算法基本原理和权值迭代公式，然后介绍了ADSP Tiger SHARC 101S芯片的基本结构特征和他强大的功能，并简单描述了其相应开发软件Visual DSP^ 3．0的功能及使用方法．给出了最小二乘恒模算法实现波束合成的具体流程图，在经过Matlab软件成功进行仿真模拟之后用Visual DSP^ 3.0设计了DSP程序，用C语言嵌套部分汇鳊语言的形式实现了用ADSP Tiger SHARC 101S进行迭代求权向量的过程。     

展望DOCSIS3．0标准

为了适应宽带网的迅猛发展,目前CableLabs已经着手开始DOCSIS 3.0版本的制定工作,DOCSIS 3.0将我们提供更高的网络接入速度。     

Nanoparticles of the Lead-free Solder Alloy Sn-3.0Ag-0.5Cu with Large Melting Temperature Depression

Due to the toxicity of lead (Pb), Pb-containing solder alloys are being phased out from the electronics industry. This has lead to the development and implementation of lead-free solders. Being an environmentally compatible material, the lead-free Sn-3.0Ag-0.5Cu (wt.%) solder alloy is considered to be one of the most promising alternatives to replace the traditionally used Sn-Pb solders. This alloy composition possesses, however, some weaknesses, mainly as a result of its higher melting temperature compared with the Sn-Pb solders. A possible way to decrease the melting temperature of a solder alloy is to decrease the alloy particle size down to the nanometer range. The melting temperature of Sn-3.0Ag-0.5Cu lead-free solder alloy, both as bulk and nanoparticles, was investigated. The nanoparticles were manufactured using the self-developed consumable-electrode direct current arc (CDCA) technique. The melting temperature of the nanoparticles, with an average size of 30 nm, was found to be 213.9°C, which is approximately 10°C lower than that of the bulk alloy. The developed CDCA technique is therefore a promising method to manufacture nanometer-sized solder alloy particles with lower melting temperature compared with the bulk alloy.