Towards implementation of a nickel silicide process for CMOS technologies

In this paper, we review some of the advantages and disadvantages of nickel silicide as a material for the electrical contacts to the source, drain and gate of current and future CMOS devices. We first present some of the limitations imposed on the current cobalt silicide process because of the constant scaling, of the introduction of new substrate geometries (i.e. thin silicon on insulator) and of the modifications to the substrate material (i.e. SiGe). We then discuss the advantages of NiSi and for each of the CoSi₂ limitations, we point out why Ni is believed to be superior from the point of view of material properties, miscibility of phases and formation mechanisms. Discussion follows on the expected limitations of NiSi and some of the possible solutions to palliate these limitations.     

Study of NiSi/Si Interface by Cross-Section Transmission Electron Microscopy

采用不同硅化工艺制备了NiSi薄膜并用剖面透射电镜(XTEM)对样品的NiSi/Si界面进行了研究.在未掺杂和掺杂(包括As和B)的硅衬底上通过物理溅射淀积Ni薄膜,经快速热处理过程(RTP)完成硅化反应.X射线衍射和喇曼散射谱分析表明在各种样品中都形成了NiSi.还研究了硅衬底掺杂和退火过程对NiSi/Si界面的影响.研究表明:使用一步RTP形成NiSi的硅化工艺,在未掺杂和掺As的硅衬底上,NiSi/Si界面较粗糙;而使用两步RTP形成NiSi所对应的NiSi/Si界面要比一步RTP的平坦得多.高分辨率XTEM分析表明,在所有样品中都形成了沿衬底硅〈111〉方向的轴延-NiSi薄膜中的一些特定晶面与衬底硅中的(111)面对准生长.同时讨论了轴延中的晶面失配问题.     

The influence of dopant species on thermal stability of NiSi film

We investigated the relationship between thermal stability of NiSi films and the implanted dopant species on Si substrates. The most stable NiSi layer appeared on Boron-implanted Si substrate, where the formation of pseudo-epitaxial transrotational structure was observed, just in case that the dose of boron is more than 5e15 atoms/cm². This unique crystallographic orientation of NiSi film on Boron-implanted substrate is a key role of thermal stability because thermal stress at grain boundary can be diminished by peculiar arrangement of transrotational domains, owing to the anisotropy in coefficient of thermal expansion (CTE) of NiSi.     

金属Ni诱导横向晶化的结构及工艺进程的优化

研究了用Ni进行金属诱导横向晶化(MILC)制备大尺寸多晶硅晶粒的结构改进和工艺条件优化,改进了MILC的结构,通过在埋层氧化层上开出与衬底相连的籽晶区,减少了大晶粒多晶硅中的缺陷分布;同时在前人的基础上优化了退火温度及时间,用Secco腐蚀液观察了晶粒大小和间界分布,最后得到了质量更好的大晶粒多晶硅,其大小在70～80μm左右.同时讨论了MILC后生成的NiSi2的去除方法,成功地去除了高温退火后生成的NiSi2,大大减小了Ni在多晶硅层中的分布,保证了将MILC方法成功应用于实现深亚微米器件的研究中.     

Ni/Pd/Si固相反应及NiSi热稳定性增强研究

研究了Ni/Pd双层薄膜在硅衬底上的硅化物形成过程.结果表明,加入Pd层后,退火形成Ni1-xPdxSi固熔体,该固熔体比NiSi的热稳定性好,使得NiSi向NiSi2的转变温度升高.加入Pd的量越多,NiSi2的成核温度越高,并用经典成核理论解释了该现象.     

掺Pt对Si(100)上形成的NiSi薄膜应力的影响

利用在线应力测试技术表征了掺入Pt后对镍硅化物薄膜应力性质的影响.通过改变NiSi薄膜中Pt含量以及控制热处理的升温、降温速率实时测量了薄膜应力,发现在Si(100)衬底上生长的纯NiSi薄膜和纯PtSi薄膜的室温应力主要是热应力,且分别为775MPa和1.31GPa,而对于Ni1-xPtxSi合金硅化物薄膜,室温应力则随着Pt含量的增加而逐渐增大.应力随温度变化曲线的分析表明,Ni1-xPtxSi合金硅化物薄膜的应力驰豫温度随Pt含量的增加,从440℃(纯NiSi薄膜)升高到620℃(纯PtSi薄膜).应力驰豫温度的变化影响了最终室温时的应力值.     

Nickel silicide formation on Si(100) and Poly-Si with a presilicide N2 + implantation

The key feature of this study is to incorporate N₂ ⁺ implant prior to Ni sputtering on the poly-Si gate and source/drain regions. The results show that the incorporation of the presilicide N₂ ⁺ implant is able to suppress agglomeration in the Ni silicide films up to 900°C and enhance the phase stability of NiSi on Si(100) up to 750°C. Stable and low sheet resistance was achieved on the silicided undoped poly-Si up to 700°C due to reduced layer inversion, which is driven by grain boundary energy and the surface energy of the poly-Si.     

金属Ni诱导横向晶化的结构及工艺进程的优化

研究了用Ni进行金属诱导横向晶化(MILC)制备大尺寸多晶硅晶粒的结构改进和工艺条件优化,改进了MILC的结构,通过在埋层氧化层上开出与衬底相连的籽晶区,减少了大晶粒多晶硅中的缺陷分布;同时在前人的基础上优化了退火温度及时间,用Secco腐蚀液观察了晶粒大小和间界分布,最后得到了质量更好的大晶粒多晶硅,其大小在70～80μm左右.同时讨论了MILC后生成的NiSi2的去除方法,成功地去除了高温退火后生成的NiSi2,大大减小了Ni在多晶硅层中的分布,保证了将MILC方法成功应用于实现深亚微米器件的研究中.     

Investigation of high-K gate stacks with epitaxial Gd2O3 and FUSI NiSi metal gates down to CET=0.86 nm

Novel gate stacks with epitaxial gadolinium oxide (Gd₂O₃) high-k dielectrics and fully silicided (FUSI) nickel silicide (NiSi) gate electrodes are investigated. Ultra-low leakage current densities down to 10^–7 A cm^–2 are observed at a capacitance equivalent oxide thickness of CET=1.8 nm. The influence of a titanium nitride (TiN) capping layer during silicidation is studied. Furthermore, films with an ultra-thin CET of 0.86 nm at a Gd₂O₃ thickness of 3.1 nm yield current densities down to 0.5 A cm⁻² at V_g=+1 V. The extracted dielectric constant for these gate stacks ranges from k=13 to 14. These results emphasize the potential of NiSi/Gd₂O₃ gate stacks for future material-based scaling of CMOS technology.     

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi₂ were possible for thicker films depending on anneal temperature and time. Activation energy of 2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi₂ is higher than for morphological degradation.