具有HfN/HfO2栅结构的p型MOSFET中的负偏置-温度不稳定性研究

研究了HfN/HfO₂高K栅结构p型金属-氧化物-半导体(MOS)晶体管(MOSFET)中，负 偏置-温度应力引起的阈值电压不稳定性(NBTI)特征.HfN/HfO₂高K栅结构的等效 氧化层厚度(EOT)为1.3nm，内含原生缺陷密度较低.研究表明，由于所制备的HfN/HfO₂ 高K栅结构具有低的原生缺陷密度，因此在p-MOSFET器件中观察到的NBTI属HfN/HfO2高K栅结构的本征特征，而非工艺缺陷引起的；进一步研究表明，该HfN/HfO₂高K栅结构中观察到的NBTI与传统的SiO₂基栅介质p-MOSFET器件中观察 到的NBTI具有类似的特征，可以被所谓的反应-扩散(R-D)模型表征： HfN/HfO₂ 栅结构p-MOSFET器件的NBTI效应的起源可以归为衬底注入空穴诱导的界面反应机理，即在负 偏置和温度应力作用下，从Si衬底注入的空穴诱导了Si衬底界面Si-H键断裂这一化学反应的 发生，并由此产生了Si^＋陷阱在Si衬底界面的积累和H原子在介质层内部的扩散 ，这种Si^＋陷阱的界面积累和H原子的扩散导致了器件NBTI效应的发生. 关键词： 高K栅介质 负偏置-温度不稳定性(NBTI) 反应-扩散(R-D)模型     

NBTI alleviation on FinFET-made GPUs by utilizing device heterogeneity

Recent experimental studies reveal that FinFET devices commercialized in recent years tend to suffer from more severe NBTI degradation compared to planar transistors, necessitating effective techniques on processors built with FinFET for endurable operations. We propose to address this problem by exploiting the device heterogeneity and leveraging the slower NBTI aging rate manifested on the planar devices. We focus on modern graphics processing units in this study due to their wide usage in the current community. We validate the effectiveness of the technique by applying it to the warp scheduler and L2 cache, and demonstrate that NBTI degradation is considerably alleviated with slight performance overhead.     

NBTI效应及其对集成电路设计的影响

可靠性设计是现代集成电路设计需要考虑的一个重要问题.对影响电路可靠性的一个最主要效应——P-MOSFET的NBTI效应进行了系统的介绍.给出了不同电压、温度下器件性能随时间变化趋势的最新研究成果.最后介绍了SPICE考虑器件器件退化的电路模拟流程.在器件尺寸日益缩小的今天,这些将成为集成电路设计关注的焦点.     

Hardware trojans in 3-D ICs due to NBTI effects and countermeasure

Going vertical as in 3-D IC design, reduces the distance between vertical active silicon dies, allowing more dies to be placed closer to each other. However, putting 2-D IC into three-dimensional structure leads to thermal accumulation due to closer proximity of active silicon layers. Also the top die experiences a longer heat dissipation path. All these contribute to higher and non-uniform temperature variations in 3-D IC; higher temperature exacerbates negative bias temperature instability (NBTI). NBTI degrades CMOS transistor parameters such as delay, drain current and threshold voltage. While the impact of transistor aging is well understood from the device point of view, very little is known about its impact on security. We demonstrated that a hardware intruder could leverage this phenomenon to trigger the payload, without requiring a separate triggering circuit. In this paper we provide a detailed analysis on how tiers of 3-D ICs can be subject to exacerbated NBTI. We proposed to embed threshold voltage extractor circuit in conjunction with a novel NBTI-mitigation scheme as a countermeasure against such anticipated Trojans. We validated through post-layout and Monty Carlo simulations using 45 nm technology that our proposed solution against NBTI effects can compensate the NBTI-effects in the 3-D ICs. With the area overhead of 7% implemented in Mod-3 counter, our proposed solution can completely tolerate NBTI-induced degraded threshold voltage shift of up to 60%.     

超深亚微米P+栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P⁺栅PMOSFET中的NBTI效应,首先通过实验分析了NBTI应力后器件特性及典型参数的退化,基于这些实验结果提出了一种可能的NBTI效应发生机制:即由水分子参与的Si-SiO₂界面处的电化学反应.最后从工艺的角度给出了减小和抑制NBTI效应的方法.     

Study on the recovery of NBTI of ultra-deep sub-micro MOSFETs

Taking the actual operating condition of complementary metal oxide semiconductor (CMOS) circuit into account, conventional direct current (DC) stress study on negative bias temperature instability (NBTI) neglects the detrapping of oxide positive charges and the recovery of interface states under the `low' state of p-channel metal oxide semiconductor field effect transistors (MOSFETs) inverter operation. In this paper we have studied the degradation and recovery of NBTI under alternating stress, and presented a possible recovery mechanism. The three stages of recovery mechanism under positive bias are fast recovery, slow recovery and recovery saturation.     

A 0.004% resolution & SAT<1.8 μson-chip adaptive anti-aging system using cuckoo intelligence-based algorithm in 65 nm CMOS

With the rapid growth of computational intelligence techniques, automatic age estimation has achieved efficiency and accuracy that benefited IC aging-mitigation applications. This paper proposes an adaptive anti-aging system scheme that uses an intelligent algorithm to monitor the frequency degradation of digital circuits. An on-chip reliability sensor with voltage controlled oscillator (VCO) architecture achieved the circuit's aging rate, featuring real-time monitoring and tolerance against PVT variations. Cuckoo intelligence-based algorithm with global search strategy could obtain the accuracy data, reduce the number of iterations, and improve use self-adjust efficiency. The loop circuit can be quickly corrected by precise voltage compensation to alleviate performance degradation. The test chip was fabricated in the TSMC 65-nm CMOS technology with a core area of 0.97 mm². The measurement results show that the resolution is 0.004% at 1.2 V and 27 °C and a self-adjust time (SAT) reaches about 1.8 μs with an operating frequency of 500 MHz, recovering at 10% aging-related degradation. In comparison with other related literatures, the resolution of the proposed method is improved by more than 2.5 times.     

基于故障插入的电路抗老化输入矢量生成研究

随着CMOS工艺特征尺寸的不断缩小,晶体管的老化效应严重影响了电路的可靠性,负偏置温度不稳定性(NBTI)是造成晶体管老化的主要因素之一。提出了一种基于固定故障插入的电路抗老化输入矢量生成方法,在电路的合适位置插入固定故障,通过自动测试向量生成(ATPG)工具获取较小的备选抗老化矢量集合,再从中筛选出最优矢量。由该方法生成的输入矢量可以使电路在待机模式下处于最大老化恢复状态,同时具有较小的时间开销。在ISCAS85电路中的仿真结果表明,与随机矢量生成方法相比,在电路待机模式下加载本文方法生成的输入矢量,可以达到最高17%的电路老化时延改善率。     

A comparative study on performance and reliability of 32-bit binary adders

In this paper, the performance and reliability of different binary adder families are studied for both the superthreshold and the near-threshold regions of operation. The adder structures are selected from both the carry propagate adders (CPAs) and parallel prefix adders (PPAs). The performance parameters which are used in the comparative study include delay, power, energy, and energy-delay-product (EDP) of the adders. Additionally, the impacts of the process variation and negative bias temperature instability (NBTI) on the delays of the adders under the aggressive supply voltage scaling are investigated. Also, the efficacies of the adders are compared using a merit function based on their performance and reliability parameters for a wide range of supply voltage levels, from the nominal voltage down to the near-threshold voltage. The study is performed for the 32-bit adder structures designed based on the 14-nm FinFET and 45-nm bulk CMOS technologies. The results which are obtained using HSPICE simulations, reveal that the reliability parameters similar to the performance parameters are a function of the adder architectures and those are the key components to determine the efficiencies of the adders. Also, the results show that the impacts of the process variation and NBTI on the delays of the high performance PPA structures are more than those of the CPA structures for the whole range of the supply voltage. The PPAs, however, have the higher merit factors compared to the CPAs under a wide range of supply voltage levels. The results presented in this paper may provide some guidelines for the designers to select proper adder structures based on their design requirements and constraints.