Indirect test of M-S circuits using multiple specification band guarding

Testing analog and mixed-signal circuits is a costly task due to the required test time targets and high end technical resources. Indirect testing methods partially address these issues providing an efficient solution using easy to measure CUT information that correlates with circuit performances. In this work, a multiple specification band guarding technique is proposed as a method to achieve a test target of misclassified circuits. The acceptance/rejection test regions are encoded using octrees in the measurement space, where the band guarding factors precisely tune the test decision boundary according to the required test yield targets. The generated octree data structure serves to cluster the forthcoming circuits in the production testing phase by solely relying on indirect measurements. The combined use of octree based encoding and multiple specification band guarding makes the testing procedure fast, efficient and highly tunable. The proposed band guarding methodology has been applied to test a band-pass Butterworth filter under parametric variations. Promising simulation results are reported showing remarkable improvements when the multiple specification band guarding criterion is used.     

A highly dependable self-adaptive mixed-signal multi-core system-on-chip architecture

In this paper we propose a design of a dependable self-organizing and adaptive mixed-signal SoC. We introduce an Artificial Hormone System (AHS) as a general control mechanism, which addresses the goals of organic computing methodology. Regarding the coexistence of digital and analog components in SoCs, we developed two new AHS implementations, one pure analog approach and one mixed-signal approach. Besides the basics of the hormone based control mechanisms, especially for the analog domain, this paper adapts the AHS upon mixed-signal SoC and presents the evaluation of a completely simulated AHS-controlled SoC. This evaluation verifies the approaches including stability issues as well as upper timing bounds and shows the improvement achieved on the system reliability. We also state the advantages from the hormone system compared to other approaches, as well as the strong points of the different hormone systems to one another.     

CMOL: Second life for silicon?

This is a brief review of the recent work on the prospective hybrid CMOS/nanowire/nanodevice (“CMOL”) circuits including digital memories, reconfigurable Boolean-logic circuits, and mixed-signal neuromorphic networks. The basic idea of CMOL circuits is to combine the advantages of CMOS technology (including its flexibility and high fabrication yield) with the extremely high potential density of molecular-scale two-terminal nanodevices. Relatively large critical dimensions of CMOS components and the “bottom-up” approach to nanodevice fabrication may keep CMOL fabrication costs at affordable level. At the same time, the density of active devices in CMOL circuits may be as high as 10¹² cm² and that they may provide an unparalleled information processing performance, up to 10²⁰ operations per cm² per second, at manageable power consumption.     

Hard-Fault Detection and Diagnosis During the Application of Model-Based Data Converter Testing

The concept of model-based test was developed in order to reduce the production test effort for data converters (Cherubal and Chatterjee (IEEE Trans Circuits Syst part I 50(3):317–327, 2003); Stenbakken and Souders (1985) Modelling and test point selection for data converter testing. In: ITC, Int Test Conf, pp 813–817; Wegener and Kennedy (IEEE Trans Circuits Syst I 51(1):213–217, 2004); Wrixon and Kennedy (IEEE Trans Instrum Meas IM-48(5):978–985, 1999)). In applying this concept, a vector of model parameters is determined for each device under test (DUT). Typically, this model parameter vector is merely used to calculate the DUT performance characteristic which is then subject to specification-oriented testing. However, each element of the model parameter vector represents an independent error source which contributes to performance degradations; thus, the model parameter vector can be viewed as a signature of the error sources. In this work, analyzing the error source signature is used to devise a model-based methodology for hard-fault detection and diagnosis. We investigate conditions under which hard-faults are detectable/diagnosable in spite of masking effects due to manufacturing process variations. In particular, we show that taking the model parameter vector as the fault signature is optimal as it minimizes the masking effects and thus maximizes detectability/diagnosibility.

重掺杂型混合信号集成电路衬底的噪声模型研究

应用器件模拟软件SILVACO模拟三种结构重掺杂型衬底中注入高频电流的分布,根据模拟结果分析得出重掺杂型衬底的简化模型为一单节点,进而将简化模型与实际的混合信号集成电路结合,建立起重掺杂型衬底的噪声模型,并给出了参数估算式。     

Oscillation-based test in bandpass oversampled A/D converters

This paper extends a study performed by the authors in previous papers dealing with the OBT approach applied to low-pass modulators ‘Microelectron. J. 33/10 (2002) 799’, showing herein the specific features associated to the bandpass case. A practical feedback strategy will be proposed in order to built an effective oscillator, which can be valuable for testing purposes. Critical points of the proposed OBT solution will be considered in order to establish useful guidelines to apply this test approach to generic bandpass ΣΔ modulators.     

Behavioral test generation modeling approach for mixed-signal IC verification

An application of behavioral modeling for mixed-signal test generation and applied results are presented. It is shown that test debugging can be provided in the verification test system before silicon by utilizing simulated behavioral mixed-signal models. Due to the behavioral modeling technique, the computational performance was enhanced to a level allowing efficient test development and debugging. Influence on efficiency in design methods is reported.     

Testing analog circuits using spectral analysis

In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.     

A feed-forward time-multiplexed neural network with mixed-signal neuron-synapse arrays

A new time-multiplexed architecture is proposed for mixed-signal neural networks. MRIII is used for training the network which is more robust for implementing mixed-signal designs. The problem of node addressing and routing for implementing the MRIII is solved by performing the operations in current mode and using a counter. Arrays of mixed-signal multiplying-digital-to-analog (MDAC) blocks are used for synaptic multiplication. A compact architecture with a more linear transfer function is proposed for the MDAC to reduce the area, power consumption and noise. The proposed network is implemented using TSMC CMOS 0.18 μ technology. The results of an XOR (2-2-1) network are presented to show the generality of the design.