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1.
1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm2 is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm2 array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall Vmin of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances. 相似文献
2.
Dong‐Wook Kim 《ETRI Journal》2006,28(1):84-86
This letter presents a small‐sized, high‐power single‐pole double‐throw (SPDT) switch with defected ground structure (DGS) for wireless broadband Internet application. To reduce the circuit size by using a slow‐wave characteristic, the DGS is used for the quarter‐wave (°/4) transmission line of the switch. To secure a high degree of isolation, the switch with DGS is composed of shunt‐connected PIN diodes. It shows an insertion loss of 0.8 dB, an isolation of 50 dB or more, and power capability of at least 50 W at 2.3 GHz. The switch shows very similar performance to the conventional shunt‐type switch, but the circuit size is reduced by about 50% simply with the use of DGS patterns. 相似文献
3.
分析了MOSFET误导通产生的原因,分别从原理和理论推导两个方面作了分析,主要考虑了开关管中寄生参数对开关特性的影响。通过求解误导通发生的条件,得到哪些参数会导致误触发,最后给出了仿真。文中还提出如何避免MOSFET误导通产生,以及改进方法,对减少实际应用中MOSFET破坏性损坏有一定意义。 相似文献
4.
A self-assembly patterning method for generation of epitaxial CoSi2 nanostructures was used to fabricate 50 nm channel-length MOSFETs. The transistors have either a symmetric structure with Schottky source and drain or an asymmetric structure with n+-source and Schottky drain. The patterning technique is based on anisotropic diffusion of Co/Si atoms in a strain field during rapid thermal oxidation. The strain field is generated along the edges of a mask consisting of 20 nm SiO2 and 300 nm Si3N4. During rapid thermal oxinitridation (RTON) of the masked silicide structure, a well-defined separation of the silicide layer forms along the edge of the mask. These highly uniform gaps define the channel region of the fabricated device. The separated silicide layers act as metal source and drain. A poly-Si spacer was used as the gate contact. The asymmetric transistor was fabricated by ion implantation into the unprotected CoSi2 layer and a subsequent out-diffusion process to form the n+-source. I–V characteristics of both the symmetric and asymmetric transistor structures have been investigated. 相似文献
5.
宽带DDS跳频源设计 总被引:1,自引:0,他引:1
直接数字合成(DDS)简单可靠、控制方便,具有很高的频率分辨率,高速转换,非常适合快速跳频的要求。在对DDS基本原理进行了简要介绍和分析后,提出宽带跳频源设计方案。 相似文献
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研究了深亚微米PD和FD SOI MOS器件遭受热截流子效应(HCE)后引起的器件参数退化的主要差异及其特点,提出了相应的物理机制,以解释这种特性。测量了在不同应力条件下最大线性区跨导退化和闽值电压漂移,研究了应力Vg对HCE退化的影响,并分别预测了这两种器件的寿命,提出了10年寿命的0.3μm沟长的PD和FD SOI MOS器件所能承受的最大漏偏压。 相似文献
9.
介绍了医用红宝石激光器触摸屏控制系统的基本结构,分析了医用红宝石激光器中主要电磁干扰(EMI)的产生机制,提出了具体的电磁兼容(EMC)技术措施并得到实验验证。 相似文献
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