基于MSP430单片机半平衡桥RLC测量仪设计

介绍了一种基于 MSP430 单片机的 RLC 测量仪的设计与实现.测量仪采用MSP430单片机为中心控制器,用未知元 件(R,L,C)与基准电阻串联作为一个半桥,MDAC TLC7524 作为另一个半桥,MSP430 单片机控制 DDS 芯片 AD9851 产生频率 可调的驱动信号驱动这两个并联的半桥,通过单片机调节...     

一个用于12位40-MS/s低功耗流水线ADC的MDAC电路设计

文中设计了一个用于12位40MHz采样率低功耗流水线ADC的MDAC电路.通过对运放的分时复用,使得一个电路模块实现了两级MDAC功能,达到降低整个ADC功耗的目的.通过对MDAC结构的改进,使得该模块可以达到12bit精度的要求.通过优化辅助运放的带宽,使得高增益运放能够快速稳定.本设计在TSMC0.35μmmixsignal3.3V工艺下实现,在40MHz采样频率下,以奈奎斯特采样频率满幅(Vpp=2V)信号输入,其SINAD为73dB,ENOB为11.90bit,SFDR为89dB.整个电路消耗的动态功耗为9mW.     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

A feed-forward time-multiplexed neural network with mixed-signal neuron-synapse arrays

A new time-multiplexed architecture is proposed for mixed-signal neural networks. MRIII is used for training the network which is more robust for implementing mixed-signal designs. The problem of node addressing and routing for implementing the MRIII is solved by performing the operations in current mode and using a counter. Arrays of mixed-signal multiplying-digital-to-analog (MDAC) blocks are used for synaptic multiplication. A compact architecture with a more linear transfer function is proposed for the MDAC to reduce the area, power consumption and noise. The proposed network is implemented using TSMC CMOS 0.18 μ technology. The results of an XOR (2-2-1) network are presented to show the generality of the design.     

A 10-bit 80-MS/s opamp-sharing pipelined ADC with a switch-embedded dual-input MDAC

A 10-bit 80-MS/s opamp-sharing pipelined ADC is implemented in a 0.18-μm CMOS.An opampsharing MDAC with a switch-embedded dual-input opamp is proposed to eliminate the non-resetting and successive-stage crosstalk problems observed in the conventional opamp-sharing technique.The ADC achieves a peak SNDR of 60.1 dB(ENOB = 9.69 bits) and a peak SFDR of 76 dB,while maintaining more than 9.6 ENOB for the full Nyquist input bandwidth.The core area of the ADC is 1.1 mm~2 and the chip consumes 28 mW with a 1.8 V power supply.     

一种用于12位40MS/s流水线ADC的宽输入摆幅MDAC

设计了一个用于12位40 MS/s流水线A/D转换器的MDAC电路.为了实现这一较高精度,对传统1.5位/级电路的传输特性进行改进.在改进后电路的传输特性中,当输入信号摆幅加倍时,输出信号摆幅与传统结构相比保持不变,这样既提高了电路信噪比,又不增加运放设计的难度.另外,还设计了实现改进传输特性的电路结构.该MDAC采用TSMC 0.35μm 3.3 V工艺设计,以奈奎斯特频率采样时,仿真结果显示,电路的输入摆幅可达到输出摆幅的两倍,SINAD为73.4dB,ENOB为11.9位,SFDR为89.0 dB.与传统结构相比,EN0B和SFDR分别提高0.7位和7.7 dB.     

一种12bit流水线型模数转换器的研究与设计

本文设计和研究了一种低功耗12Bit 流水线模数转换器的结构,其采用了TSMC 0.18um工艺设计,3.3V单电源电压,5MHz采样率,动态范围为1V,INL为0.5LSB,DNL为2LSB,通过详细的电路原理分析和软件Cadence的仿真,并流片测试,性能达到设计初衷。     

一种优化的应用于无线通信模拟前端的模数转换器

本文基于无线通信模拟前端的特点,设计一个优化的10bit 80MS/s 的模数转换器。不同于传统的1.5bit每级的流水线结构,本设计实现2.5bit每级的优化结构。片上的低噪声参考电压缓冲器有利于实现SoC集成,宽带宽摆幅采样保持电路有利于在高输入信号频率条件下取得良好的动态性能。在0.18μm 1P6M的工艺平台上实现该设计,芯片核心面积为0.85mm₂. 测试结果表明,该模数转换器获得ENOB=9.4bit,SFDR=72dBc的性能。     

Foreground calibration technique of a pipeline ADC using capacitor ratio of Multiplying Digital-to-Analog Converter (MDAC)

A foreground calibration technique of a pipeline analog-to-digital converter (ADC) has been presented in this paper. This work puts an emphasis on erroneous ADC output occurring due to device mismatch, which, in any standard CMOS process boils down to capacitor mismatch. Deviation of gain of a multiplying digital-to-analog converter (MDAC), also known as the radix of a pipeline ADC stage, from its ideal values adds to the non-linearity of the ADC output. Capacitor mismatch is a major contributor for such an error. The proposed foreground calibration technique makes use of a simple arithmetic unit to extract the radix value from the ADC output for calibration. It uses a sinusoidal signal at the input for calibration purposes. The input sinusoidal signal can be sampled by the ADC clock at any rate for the calibration algorithm to be successful. Behavioral simulation of a pipeline ADC with 5% capacitor mismatch supports the established technique. To verify the calibration algorithm further, pipeline ADCs of different resolutions have been designed and simulated in a 0.18 μm CMOS process.     

12位20MS/s流水线ADC的研制

流水线结构是高速高精度ADC的首选.通过对流水线ADC的结构、MDAC电路进行了研究;提出新型采样保持开关;设计了12位20 MS/s采样率流水线ADC,并基于SMIC0.35μm混合CMOS工艺进行流片实现,测试结果表明,在测试仪器只有10位精度的情况下SFDR=65 dB,SNDR=56 dB,SNR=56.9 dB,ENOB=9.1 bit,最后对测试结果进行分析.