SOI LIGBT抗闩锁效应的研究与进展

概述了绝缘层上硅横向绝缘栅双极晶体管(SOI LIGBT)抗闩锁结构的改进历程,介绍了从早期改进的p阱深p+欧姆接触SOI LIGBT结构到后来的中间阴极SOI LIGBT、埋栅SOILIGBT、双沟道SOI LIGBT、槽栅阳极短路射频SOI LIGBT等改进结构;阐述了一些结构在抗闩锁方面的改善情况,总结指出抑制闩锁效应发生的根本出发点是通过降低p基区电阻的阻值或减小流过p基区电阻的电流来削弱或者切断寄生双极晶体管之间的正反馈耦合。     

CM303双二选一模拟开关电路

本文主要介绍CM303双二选一模拟开关电路的基本结构,包括从电路的版图设计、工艺设计原则,以及采用埋层外延技术,本电路以实现消除闭锁现象为目的。给出了制造工艺条件对外延材料的选择关系,最后给出了电路的性能指标。     

基于SCR的ESD保护电路防闩锁设计

SCR器件作为目前单位面积效率最高的ESD保护器件,被广泛研究并应用到实际电路中.SCR所具有的低保持电压特性可以带来很高的ESD性能,但同时也会导致闩锁.文章从提高保持电压和触发电流这两方面入手,研究在实际电路应用中如何防止ESD保护电路发生闩锁.     

CMOS存储器瞬时辐照效应规律实验研究

对超深亚微米存储器(32 k SRAM)激光辐照下的剂量率效应进行了初步研究,实验测量了SRAM激光辐照下的效应规律,比较了零时SRAM的状态(读状态和片选无效状态)对效应规律的影响,得到了一些初步的效应规律.     

Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology

The proposed device has a high holding voltage and a high triggering current characteristic. These characteristics enable latch-up immune normal operation as well as superior full chip electro-static-discharge (ESD) protection. The device has a small area in requirement robustness in comparison to gate-grounded NMOS (ggNMOS). The proposed ESD protection device is designed in 0.25 μm CMOS technology. In the experimental result, the proposed ESD clamp has a double trigger characteristic, a high holding voltage of 3.8 V and a high trigger current of greater than 120 mA. The robustness has measured to HBM 8 kV (HBM: human body model) and MM 400 V (MM: machine model). The proposed device has a high-level It2 of 52 mA/μm approximately.     

平板显示器功率驱动芯片的Latch-up及克服方法

详细分析了平板显示器驱动芯片中的Latch-up现象,在此基础上采用了一种克服Latch-up的方法:在低压部分增加多子保护环,在高低压之间增加少子保护环。借助TCAD软件详细研究了少子环位置及宽度对抗Latch-up效果的影响。实验结果证明,采用该方法可以有效地克服功率集成电路的Latch-up现象。     

CMOS结构中的闩锁效应

本文较为详细地阐述了体硅CMOS结构中的闩锁效应，分析了CMOS结构中的闩锁效应的起因，提取了用于分析闩锁效应的集总组件模型，给出了产生闩锁效应的必要条件与闩锁的触发方式。通过分析表明，只要让CMOS电路工作在安全区，闩锁效应是可以避免的，这可以通过版图设计规则和工艺技术，或者两者相结合的各种措施来实现。本文最后给出了防止闩锁效应的关键设计技术。     

Device design of single-gated feedback field-effect transistors to achieve latch-up behaviors with high current gains

In this study, a device design of single-gated feedback field-effect transistors (FBFETs) is proposed to achieve latch-up behaviors with high current gains. The latch-up mechanism is examined by conducting an equivalent circuit analysis, and the band diagram, I–V characteristics, memory window, subthreshold swing, and on/off current ratio are investigated using a commercial device simulator. The proposed FBFETs exhibit memory windows wider than 3.0 V, subthreshold swings less than 0.1 mV/decade, the on/off current ratios of approximately 10¹⁰, and on-currents of approximately 10⁻⁵ A at room temperature. The superior device characteristics and controllable memory windows open the promising possibility of FBFETs as the next-generation electronic devices.     

The transient analysis of latch-up in CMOS transmission gate induced by laser

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature.     

工艺阱深对CMOS集成电路抗闩锁性能的影响

闩锁效应是体硅CMOS电路中最为严重的失效机理之一,而且随着器件特征尺寸越来越小,使得CMOS电路结构中的闩锁效应日益突出。以P阱CMOS反相器和CMOS集成电路的工艺结构为基础,采用可控硅等效电路模型,较为详细地分析了闩锁效应的形成机理,并利用试验证实,通过加深P阱深度,可以明显提升CMOS电路的抗闩锁性能。