IRS辅助的SWIPT系统中基于能效优先的波束成形设计与优化

以智能反射面(intelligent reflecting surface,IRS)辅助的无线携能通信(simultaneous wireless information and power transfer,SWIPT)系统为背景,研究了该系统中基于能效优先的多天线发送端有源波束成形与IRS无源波束成形联合设计与优化方法。以最大化接收端的最小能效为优化目标,构造在发送端功率、接收端能量阈值、IRS相移等多约束下的非线性优化问题,用交替方向乘子法(alternating direction method of multipliers,ADMM)求解。采用Dinkelbach算法转化目标函数,通过奇异值分解(singular value decomposition,SVD)和半定松弛(semi-definite relaxation,SDR)得到发送端有源波束成形向量。采用SDR得到IRS相移矩阵与反射波束成形向量。结果表明,该系统显著降低了系统能量收集(energy harvesting,EH)接收端的能量阈值。当系统总电路功耗为?15 dBm时,所提方案的用户能效为300 KB/J。当IRS反射阵源数与发送天线数均为最大值时,系统可达最大能效。     

Developing Flexible Quinacridone-Derivatives-Based Photothermal Evaporaters for Solar Steam and Thermoelectric Power Generation

Solar-driven interfacial vaporization by localizing solar-thermal energy conversion to the air−water interface has attracted tremendous attention. In the process of converting solar energy into heat energy, photothermal materials play an essential role. Herein, a flexible solar-thermal material di-cyan substituted 5,12-dibutylquinacridone (DCN−4CQA)@Paper was developed by coating photothermal quinacridone derivatives on the cellulose paper. The DCN−4CQA@Paper combines desired chemical and physical properties, broadband light-absorbing, and shape-conforming abilities that render efficient photothermic vaporization. Notably, synergetic coupling of solar-steam and solar-electricity technologies by integrating DCN−4CQA@Paper and the thermoelectric devices is realized without trade-offs, highlighting the practical consideration toward more impactful solar heat exploitation. Such solar distillation and low-grade heat-to-electricity generation functions can provide potential opportunities for fresh water and electricity supply in off-grid or remote areas.     

超宽带大功率合成器设计北大核心CSCD

在80 MHz~1 GHz频段,单个功率管输出功率能达到100 W以上,为研制输出功率400 W的功率放大器,文中设计了四路功率合成器。该合成器需要实现功率容量大、工作频带宽、体积小的设计目标。在功率容量方面,文中采用悬置带状线结构,其功率容量远远大于微带线结构;在工作频带方面,采用切比雪夫九节阻抗变换器,将工作带宽拓宽为80 MHz~1 GHz;在体积方面,文中合成器的功率合成部分采用Y型节级联实现四路功率合成,阻抗变换部分采用切比雪夫阻抗变换器进行阻抗变换,该结构相较于磁环巴伦功率合成器,不但具有损耗小、平坦度高的优点,而且通过将阻抗变换器设计成曲折的形状,进一步缩小了合成器体积。仿真与实测结果显示该合成器在80 MHz~1 GHz范围内还具有较高的平坦度,合成效率可达90%以上。     

基于关键路径延时检测的自适应电压缩减技术

为了减小传统的最差情况设计方法引入的电压裕量,提出了一种变化可知的自适应电压缩减(AVS)技术,通过调整电源电压来降低电路功耗.自适应电压缩减技术基于检测关键路径的延时变化,基于此设计了一款预错误原位延时检测电路,可以检测关键路径延时并输出预错误信号,进而控制单元可根据反馈回的预错误信号的个数调整系统电压.本芯片采用SMIC180 nm工艺设计验证,仿真分析表明,采用自适应电压缩减技术后,4个目标验证电路分别节省功耗12.4％,11.3％,10.4％和11.6％.     

An inequality connecting entropy distance,Fisher Information and large deviations

In this paper we introduce a new generalisation of the relative Fisher Information for Markov jump processes on a finite or countable state space, and prove an inequality which connects this object with the relative entropy and a large deviation rate functional. In addition to possessing various favourable properties, we show that this generalised Fisher Information converges to the classical Fisher Information in an appropriate limit. We then use this generalised Fisher Information and the aforementioned inequality to qualitatively study coarse-graining problems for jump processes on discrete spaces.     

Semilinear wave models with friction and viscoelastic damping

In this paper, we study the global (in time) existence of small data solutions to the Cauchy problem for the semilinear wave equation with friction, viscoelastic damping, and a power nonlinearity. We are interested in the connection between regularity assumptions for the data and the admissible range of exponents p in the power nonlinearity.     

Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

Estimation of power density in IMPATT using different materials

ABSTRACT

The RF output power dissipated per unit area is calculated using Runge-Kutta method for the high-moderate-moderate-high (n⁺-n-p-p⁺) doping profile of double drift region (DDR)-based impact avalanche transit time (IMPATT) diode by taking different substrate at Ka band. Those substrates are silicon, gallium arsenide, germanium, wurtzite gallium nitride, indium phosphide and 4H-silicon carbide. A comparative study regarding power dissipation ability by the IMPATT using different material is being presented thereby modelling the DDR IMPATT diode in a one-dimensional structure. The IMPATT based on 4H-SiC element has highest power density in the order of 10¹⁰ Wm^?2 and the Si-based counterpart has lowest power density of order 10⁶ Wm^?2 throughout the Ka band. So, 4H-SiC-based IMPATT should be preferable over others for the power density preference based application. This result will be helpful to estimate the power density of the IMPATT for any doping profile and to select the proper element for the optimum design of the IMPATT as far as power density is concerned in the Ka band. Also, we have focused on variation of power density with different junction temperatures and modelled the heat sink with analysis of thermal resistances.     

Compiler compatible 5.66 Mb/mm2 8T 1R1W register file in 14 nm FinFET technology

1-read/1-write (1R1W) register file (RF) is a popular memory configuration in modern feature rich SoCs requiring significant amount of embedded memory. A memory compiler is constructed using the 8T RF bitcell spanning a range of instances from 32 b to 72 Kb. An 8T low-leakage bitcell of 0.106 μm² is used in a 14 nm FinFET technology with a 70 nm contacted gate pitch for high-density (HD) two-port (TP) RF memory compiler which achieves 5.66 Mb/mm² array density for a 72 Kb array which is the highest reported density in 14 nm FinFET technology. The density improvement is achieved by using techniques such as leaf-cell optimization (eliminating transistors), better architectural planning, top level connectivity through leaf-cell abutment and minimizing the number of unique leaf-cells. These techniques are fully compatible with memory compiler usage over the required span. Leakage power is minimized by using power-switches without degrading the density mentioned above. Self-induced supply voltage collapse technique is applied for write and a four stack static keeper is used for read Vmin improvement. Fabricated test chips using 14 nm process have demonstrated 2.33 GHz performance at 1.1 V/25 °C operation. Overall V_min of 550 mV is achieved with this design at 25 °C. The inbuilt power-switch improves leakage power by 12x in simulation. Approximately 8% die area of a leading 14 nm SoC in commercialization is occupied by these compiled RF instances.