New trends in digital circuit multiplication technology

This paper discusses the achievements and the unsolved problems of the first generation of Digital Circuit Multiplication Systems (DCMS)

1 DCMS is an abbreviation for Digital Circuit Multiplication Systems. DCME is an abbreviation for Digital Channel Multiplication Equipment. Both refer to the same technique of combining digital speech interpolation and low rate encoding.

. The following summarizes proposed improvements in DCMS technology. A major improvement in DCMS gain may be achieved by implementation of facsimile demodulation. The design considerations of this technique are discussed. The CCITT activities on standardization of a 16 kb/s speech coding algorithm are reviewed. In order to adapt this algorithm to implementation in a DCMS, the operation of the algorithm has been modified to enable variable bit rate operation at rates between 12·8 and 24 kb/s. The implementation of such an algorithm in DCMS will further increase the overall compression gain. The first generation of DCMS has been implemented mainly on heavy traffic routes. A DCMS terminal which is optimized for operation on ‘thin’, or smaller, routes, using an IDR link operating at 512 kb/s, is described. Tandem operation of DCMS is becoming an increasingly important consideration on both international and national routes. The accumulation of qdu's (quantization distortion units) when two pairs of DCME/S terminals are operated in tandem can be avoided by an arrangement without ADPCM decoding/encoding in the transit terminals so that the ADPCM decoding is carried out only at the final destination DCMS terminal.     

基于DSP实现的G.728编码语音码流能量估计算法

本文基于DSP芯片TMS320C6201提出了通过对简化G．728建议解码过程实现低复杂度的语音能量估算的算法。并成功地在TMS320C6201上进行了优化实现。     

用增益精确值和归一化波形码书改进G.728

分析研究了增益、波形乘积码书结构的缺陷，设计了归一化波形码书和精确表示增益的LD-CELP方案。采用自适应预测和自适应量化对增益的精确值进行量化，在3bit和4bit自适应量化时比G．728固定量化增益分别提高0．5dB和6dB。采用4bit自适应量化和64波形码书比G.728SNR提高约1dB。将G．728综合滤波器由50阶减少到30阶，信噪比不变而算法复杂性降低约20%。     

LD-CELP编解码器的ASIC设计

LD-CELP可以全面满足16 kb·s-1算法的性能要求,已被广泛应用在会议电视系统、IP电话等领域.基于此规范,采用Verilog HDL硬件描述语言完成RTL级设计,所有编解码结构都由Verilog实现的DSP ensine完成,并对最佳码书序号进行了压缩处理,解决了最佳码书序号的比特浪费问题.系统物理测试采用FPGA验证方式.验证结果表明,系统功能完全正确,可实现实时编解码过程,解码语音具有良好可懂度.     

15.2kb／sLD—CELP语音编码算法及实时实现

本文以Ｇ．７２８语音编码标准为基础,提出一个１５．２ｋｂ／ｓ ＬＤ－ＣＥＬＰ语音编码算法。通过对滤形码书进行重新设计,降低了算法复杂性,同时保持高质合成语音。最后,用双片ＴＭＳ３２０Ｃ３１高速ＤＳＰ系统全双工实时实现了该算法。     

基于 TMS320VC5402实现双路全双工ITU G.728语音编解码

对G．728编解码算法和定点数字信号处理芯片TMS320VC5402作了简要介绍。并讨他在TMS320VC5402上实现双路全双工ITUG7．28语音编解码的关键技术,包括软件设计方法和算法优化技术。结果表明,所运行的编解码程序,既可以保证良好的语音质量,又有良好的实时性。     

用TMS320C6211实现多路G.728语音编解码标准

ITU-TG．728建议是国际电信联盟于1992年制定的比特率为16kb／s的语音编码标准。本文扼要地介绍了G．728编解码算法的原理和TMS320C6211定点DSP芯片，并详细讨论了G．728算法在C6211上实时实现的软件开发及优化的关键技术。     

低延迟话音编码算法的增益优化与混合窗设计

G.728标准将增益滤波器的偏移不适当地处理成常数32dB,相当于将20～30ms内短时平稳的语音信号不适当地按整个时间轴上的平稳信号对待。对增益滤波器的改进必然涉及优化混合窗。该文提出一种估计平均分段信噪比的方法用来设计混合窗参数,并导出激励增益的精确表示。以此为基础,将Jayant的自适应量化与G.728的增益预测结合起来,提出一种适合于设计低时延码激励线性预测(LD-CELP)的增益码书的方案。用此方法,激励的精确值经自适应预测和量化后,3bit自适应量化和4bit自适应量化分别比G.728的固定量化有0.5dB和6dB的信噪比的改善。当采用4bit自适应量化和64码字的波形码书,比G.728复杂性降低20%,同时信噪比提高1dB。