一种脉冲编码CMOS神经元电路的设计与实现

从生物神经元的电化学特性出发,基于积分发放(I&F)电路理论模型,提出了一种新型的结构紧凑的脉冲编码CMOS神经元电路,模仿神经元细胞体输出连续脉冲串.该模型的优点在于大大简化了模型结构,其运行结果很好地拟合了神经元的生理特性,且在工艺参数不可调节的情况下,可通过输入信号灵活控制电路结构,改变输入耦合权重,从而实现对输...     

BSIM3v3模型关键参数提取的研究

BSIM3v3是现在业界普遍使用的MOSFET模型,用它仿真电路能够得到准确的结果,但这个复杂的模型给电路设计者的手算过程带来了相当大的困难.为得到更为准确的关键参数,对用HSPICE从BSIM3v3模型提取关键参数的方法进行了改进,并以一个运放设计为例进行比较,该方法提取的关键参数的手算结果比其他方法更接近仿真结果.     

Design metal-dot based QCA circuits using SPICE model

This paper proposes a SPICE model development methodology for quantum-dot cellular automata (QCA) cells and presents a SPICE model for QCA cells. The model is validated by simulating the basic logic gates such as inverter and majority voter. The proposed model makes it possible to design and simulate QCA combinational circuits and hybrid circuits of QCA and other NANO devices using SPICE. In the second half part of the paper, SET and QCA co-design methodology is proposed and SET is used as a readout interface of the QCA cell array. The SET and QCA hybrid circuit is a promising nano-scale solution.     

一种应用于AMOLED的阵列扫描控制电路

为了提高显示屏的成品率,降低成本,提出了AMOLED屏上行驱动电路的一种设计方案,以PMOS-TFT为行驱动电路的结构.该电路由阵列扫描控制电路构成,每个阵列扫描控制单元由2个时钟信号控制,并包含5个PMOS-TFT.通过HSPICE的仿真,结果得出电路的仿真结果与分析结果一致,验证了电路功能的正确性.     

共振隧穿二极管基础电路的模拟与分析

简单介绍了RTD的器件特性和器件模型 ,用HSPICE模拟出RTD与电阻、MOS晶体管、RTD本身结合的电路特性。通过对不同电路参数I V特性的模拟和分析 ,为理解RTD器件机理和构造复杂电路提供了初步的基础     

Optimizing CMOS Transconductor-C Filters for Low Power Wide Band Operation

A novel figure of merit to describe the bandwidth power efficiency of CMOS transconductors— is proposed and optimized for cross-coupled differential pair transconductor structures. The optimization is done in two different ways: univariable unconstrained and multivariable constrained. It is revealed that not only dc biases but also ac input phases can affect the bandwidth power efficiency of the transconductor. The bias voltages which can lead to best ratio at different ac phase combinations are obtained and presented in the article. HSPICE simulations are conducted to verify the theoretical predictions. On the basis of the cross-coupled differential pair transconductor, a biquadratic transconductor-C filter configuration is implemented. The frequency vs. power characteristic of the filter is studied for both optimally- and non-optimally-biased transconductor. It is shown that the optimization of the transconductor structure can result in performance improvement of the transconductor-C filter. The deviation of the optimal bias condition between the transconductor alone and the transconductor-C filter due to the inclusion of peripheray circuitries in the filter is discussed in the article.     

一种有效的系统芯片串扰故障激励检测模型

目前的系统芯片(SOC)制造技术已经进入了深亚微米时代,由于系统芯片内部信号传输线发生串扰而导致系统功能失效的串扰故障问题不容忽视。文中在对系统芯片中信号传输线的串扰产生性质进行深入研究的基础上,提出一种简单有效的系统芯片串扰故障激励检测模型——基于搜索的MAF模型。对使用这种串扰故障激励模型的效率和已有的MAF模型进行了对比。结果显示在串扰较弱时,其所需的检测矢量数和已有的MAF模型相当;而在串扰较严重时,这种新的串扰故障激励检测模型只需较少的激励检测矢量即可以完成对所有串扰故障的激励检测。     

Modeling and simulation of combinational CMOS logic circuits by ANFIS

In this paper, application of adaptive neuro-fuzzy inference system (ANFIS) in modeling of CMOS logic gates as a tool in designing and simulation of CMOS logic circuits is presented. Structures of the ANFIS are developed and trained in MATLAB 7.0.4 program. We have used real hardware data for training the ANFIS network. A hybrid learning algorithm consists of back-propagation and least-squares estimation is used for training. Influence of the structure of the proposed ANFIS model on accuracy and network performance has been analyzed through some combinational circuits. For the comparison of the ANFIS simulation results, we have simulated the circuits in HSPICE environment with 0.35 μm process nominal parameters. The comparison between ANFIS, HSPICE, and real hardware shows the feasibility and accuracy of the proposed ANFIS modeling procedure. The results show the proposed ANFIS simulation has much higher speed and accuracy in comparison with HSPICE simulation and it can be simply used in software tools for designing and simulation of complex CMOS logic circuits.     

Robust HSPICE modeling of a single electron turnstile

This paper presents a novel HSPICE circuit model for designing and simulating a single-electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE model consists of two nearly similar parts whose operations are independent of each other; this disjoint feature permits the accurate and reliable modeling of the sequential transfer of electrons through the turnstile in the storage node (modeled on a voltage level basis). It therefore avoids the transient (current-based) nature of a previous model, thus ensuring robustness in simulated operation. The model has been simulated and results show that it can robustly operate at 32 and 45 nm with excellent stability in its operation. Extensive simulation results are presented to substantiate the advantages of using the proposed model with respect to changes in the circuit model parameters as related to capacitances, feature size and voltages.     

Modeling and simulation of carbon nanotube field effect transistor and its circuit application

The carbon nanotube field effect transistor (CNTFET) is modelled for circuit application. The model is based on the transport mechanism and it directly relates the transport mechanism with the chirality. Also, it does not consider self consistent equations and thus is used to develop the HSPICE compatible circuit model. For validation of the model, it is applied to the top gate CNTFET structure and the MATLAB simulation results are compared with the simulations of a similar structure created in NanoTCAD ViDES. For demonstrating the circuit compatibility of the model, two circuits viz. inverter and SRAM are designed and simulated in HSPICE. Finally, SRAM performance metrics are compared with those of device simulations from NanoTCAD ViDES.