Voltage reference architectures for low-supply-voltage low-power applications

This paper presents a voltage reference generator architecture and two different realizations of it that have been fabricated within a standard 0.18 μm CMOS technology. The architecture takes the advantage of utilizing a sampled-data amplifier (SDA) to optimize the power consumption. The circuits achieve output voltages on the order of 190 mV with temperature coefficients of 43 ppm/°C and 52.5 ppm/°C over the temperature range of 0 to 120°C without any trimming with a 0.8 V single supply. The power consumptions of the circuits are less then 500 nW while occupying an area of 0.2 mm² and 0.08 mm², respectively.     

一种漂移室定位子性能反常现象的研究

研究了一种漂移室定位子性能的反常现象,它关系到定位子的使用寿命．着重测量了暗电流和随机噪声与时间、高压及温度的关系.     

Theory of a novel voltage-sustaining layer for power devices

The theory of a novel voltage-sustaining layer for power devices, called a Composite Buffer layer (CB-layer for short) is proposed. The CB-layer can be implemented in several ways, one particular implementation is used here, which consists of alternating n- and p-type regions, that are parallel to the direction of the applied electric field. In the off-state, the fields induced by the depletion charges of both region types compensate each other to allowing the doping in both n-regions and p-regions to be very high without causing a reduction of the breakdown voltage. In the onstate the heavy doping ensures the voltage drop is very low and that the saturation current density high. A simple relationship between the specific on-resistance and R_on and the sustaining voltage V_B can be shown to be R_on=2.53 × 10⁻⁷bV_B^1.23 ωcm², where the breadth b (in μm) of each region is much smaller than the thickness W. The design method of the CB-layer is discussed in some detail. The simulation results are shown to be in perfect agreement with the theory. The structure has application to a wide variety of different power devices. An RMOST structure has been used to demonstrate the benefits of the technique in the paper, for which excellent performance is demonstrated.     

多功能保护与告警自动调压装置

本文叙述了作者设计并制作的具有多种告警和保护功能的３８０Ｖ交流自动调压器的控制装置。它可使调压精度提高到工作电压的士１％以内，并在自动调压器输出电压过高或过低时、或出现故障时进行告警。当出现故障或误动作时自动切断调压电动机的电源。     

一种延长FU—113管子寿命的简单而有效的方法

维护大功率电子管和延长其使用寿命,对保障电视发射机稳定、安全、可靠地工作和节约资金都起着重要作用。本文重点从理论上分析了如何延长大功率管的寿命,以及怎样才能在实际电路中实施这一方案。     

电子应用产品的防电击试验浅析

本文依据国家有关标准对电子应用产品的防电击试验进行了简介和分析，指出了试验中应注意的问题。     

Liquid crystal lens with focus movable in focal plane

A liquid crystal lens with focus movable in the focal plane is reported. There are three electrodes in the cell. One electrode with a hole in the center is divided into four subelectrodes. The potential of each subelectrode is adjusted to produce a desired asymmetrical phase transformation resulting in off-axis movement of the focus. The potential of another electrode is adjusted to maintain the focus in the focal plane. Movements of the focus in three directions in the focal plane are demonstrated experimentally, and off-axis movement as large as approximately 800 μm is realized.     

Electrochemistry of capillary systems with narrow pores. IV. Dialysis potentials

The dialysis potentials of different collodion membranes with graded pore sizes and electrochemical activities have been measured in dilute aqueous KCl solutions as functions of concentration. It is possible to predict the value of the diffusion potential within a few millivolts on the basis of electrical conductivity data obtained with the same membranes. In general, the measured values are lower than those calculated. It is assumed that this difference is caused by the membranes having a distribution of pore sizes.     

Assessing the width of Gaussian density of states in organic semiconductors

The Density of States (DOS) is an ingredient of critical importance for the accurate physical understanding of the optoelectronic properties of organic semiconductors. The disordered nature of this class of materials, though, renders the task of determining the DOS far from trivial. Its extraction from experimental measurements is often performed by driving the semiconductor out of thermal equilibrium and therefore requires making assumptions on the charge transport properties of the material under examination. This entanglement of DOS and charge transport models is unfavorable since transport mechanisms in organic semiconductors are themselves still subject of debate. To avoid this, we propose an alternative approach which is based on populating and probing the DOS by means of capacitive coupling in Metal Insulator Semiconductors (MIS) structures while keeping the semiconductor in thermal equilibrium. Assuming a Gaussian shape, we extract the DOS width by numerical fitting of experimental Capacitance–Voltage curves, exploiting the fact that the DOS width affects the spatial distribution of accumulated charge carriers which in turn concurs to define the MIS capacitance. The proposed approach is successfully tested on two benchmark semiconducting polymers, one of n-type and one of p-type and it is validated by verifying the robustness of the extraction procedure with respect to varying the insulator electrical permittivity. Finally, as an example of the usefulness and effectiveness of our approach, we study the static characteristics of thin film transistors based on the aforementioned polymers in the framework of the Extended Gaussian Disorder transport model. Thanks to the extracted DOS widths, the functional dependence of current on the gate voltage is nicely predicted and physical insight on transistor operation is achieved.     

Process variability-induced NoC link failure: A probabilistic model

As technology scales down, the amount of process variations increases causing Networks-on-Chip (NoC) links, designed to be identical, to have current and delay variations. Thus, some links may fail to meet design timing or power constraints. Using current and delay variations with design constraints, we estimate link failure probability across NoC links. Modeling results show that the average NoC link failure probability across a 4×4 mesh reaches 3.3% for voltage mode (VM) links and 3.7% for current mode (CM) links at 32 nm. The average NoC link failure probability also increases as the supply voltage decreases or the operating frequency increases. As NoC mesh size scales from 4×4 to 8×8, the link failure probability doubles to 8% for VM links at 22 nm. Topology evaluation shows that for small NoC size, the grid topology outperforms the tree one with lower amount of variation. On the other hand, for relatively large NoC sizes, the hierarchical tree and ring topologies outperform the grid topology with lower amount of variations across the links.